Two-Dimensional Device Simulation of the InGaAs/InP Avalanche Photodiodes

The high gain, and high gain-bandwidth product of the avalanche photodiodes is one of the key device for the long distance optical communication systems. For the 0.92-1.65um wavelength range, the narrow bandgap materials, like InGaAs(0.77eV), are used as the absorption medium. And the breakdown location is a major issue to design of the APD’s. In order for the device to operate with high gain and low noise[1], the design of the guard ring to suppress edge breakdown is important.

Resistor and Capacitor L/W Parameters in LVS Comparison

In the design of VLSI circuits the situations occur very often when a single schematic device is implemented in the layout by the group of several devices connected in parallel or series. Such groups of devices must be reduced to a single device in the layout and the circuits must be compared in terms of the single devices taking into account their geometrical characteristics. In this article we introduce some methods of calculation and comparison of geometrical parameters of resistors and capacitors connected in parallel or series, when LVS verification is performed.

Fast and Accurate Simulation of the Steady-State of Voltage Controlled Oscillators with SmartSpice-RF

A novel simulation method of the steady-state of oscillators, based on Harmonic Balance (HB), is presented. A comparison with regular transient simulations demonstrates its advantages on a feedback voltage-controlled oscillator (VCO).

A Sophisticated Verilog-A Debugger

During the elaboration of a Verilog-A model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO Verilog-A debugger has been designed to meet these needs. It is available since version 2.6.0.R of SmartSpice and works along with SILVACO C-Interpreter. It allows iteration-per-iteration Verilog-A modules debugging. The debugger is tracing all the Verilog-A instantiations of the design, either instances of the SmartSpice netlist or in other Verilog-A modules.

Noise Simulations

If the MOS model file has the parameters: noia, noib, noic, Af, Kf and nlev=0 will SmartSpice ignore the BSIM III noise parameters (noia, noib and noic)

EDIF Conversion Flow on Gateway

EDIF has been a vital part of the Electronic Design Automation (EDA) industry for many years and Gateway allows users to convert edif200 formatted files of other tools vendors into Gateway’s schematics and symbols.

Hipex-CRC Parasitic RC-Network Reducer

Design of large scale chips requires precise knowledge of interconnect delays. However, detailed analysis of interconnects may quickly become computationally too expensive due to the distributed nature of the networks, and the large number of internal nodes extracted.

SET Accurate Compact Model for SET-MOSFET Hybrid Circuit Simulation

Single-Electron Transistors (SETs) [1][2] are attractive candidates for post-CMOS VLSI ICs. Accurate models are also required in order to efficiently design SET circuits and hybrid circuits

Generic Devices – The New HIPEX-NET Feature for Extraction of Custom Devices

Hipex-NET is SILVACO’s powerfull hierarchical layout netlist extractor. Built-in extracting rules permit to make fast and accurate parameter extraction for basic set of devices as MOS, BJT, diode, capacitor and resistor. But these rules can’t descibe all devices features and parameters that appeare in new submicron or RF layout designs. To resolve this problem the new HIPEX-NET command HIPEX GENERIC_DEVICE has been introduced. This new HIPEX-NET feature gives to user the capability to extract not only additional parameters for standard devices but also custom defined devices with arbitrary set of parameters. This article describes the new HIPEX-NET command.

How can I become a more efficient user of Expert?

How can I become a more efficient user of Expert?