It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation. Each SEU statement can locate a strike anywhere in the semiconductor and at any time during the transient, offering a range of simulation possibilities. One possible use for simulating multiple SEU strikes is for simulating spallation events, where a high energy particle, such as a cosmic ray, suffers a nuclear interaction, producing one or more different sources of ionizing particle at the nuclear reaction site. In this article, we will, demonstrate two SEU strikes in different locations at two different times on a full six transistor 22nm SRAM cell, including four layers of metal interconnect.

The Victory Process cell mode Delaunay 3D device meshing algorithm already includes various TCAD-based local refinement algorithms to ensure accurate and robust device simulation. These include junction and interface distance refinement. One benefit of these approaches is that complex refinement behavior can be specified via a simple deck interface, but a limitation is that the results can only vary according to the small number of parameters of the schemes. In some cases, such as particle path refinement, it can be useful to have finer, more local control over the mesh and the shape distance refinement schemes have been produced to support this.

Calculation of light extraction efficiency or optical output coupling efficiency is often needed in simulating a light emitting device (LED) such as an organic LED (OLED). It is best to perform these calculations without running electrical simulation in the device, as parameters for new materials are hard to obtain and generally unnecessary in calculating light extraction efficiency. Moreover, a pure optical simulation will save simulation time and avoid any potential un-convergence in the electrical simulation.

Silicon carbide is expected to be an excellent device material as high voltage and low-loss power devices. Recently, SBD (Schottky Barrier Diode) and MOSFET based on silicon carbide have been realized [1-3], however, those devices have some problems for its reliability and control of the IV characteristics. The problems are related to defects in the bulk and at the interface of insulator/semiconductor. The concentration (~5e12[/cm3]) of the defects is 2 orders higher than that of silicon [4], and so the defects cause degradation of device characteristics. The investigation of the defect property is important for the improvement of the device performance.