• Analog Cores

Silvaco offers a suite of high-performance and low-power analog IP solutions for Samsung Foundry.

Title Features
Samsung Foundry
28nm
FD-SOI
14 nm
11 nm
10 nm
8 nm
Integer
PLL
1.2 GHz
PDF
2.0 GHz
PDF
2.4 GHz
PDF
2.5 GHz
3.2 GHz
PDF
4.3 GHz
PDF
4.5 GHz
Fractional-N SSC
PLL
1.2 GHz
PDF
2.5 GHz
3.2 GHz
PDF
4.5 GHz
Low Jitter
PLL
100 MHz
PDF
640 MHz
PDF
ADC 12 bit, 1.0 MSPS, 16-ch
PDF
12 bit, 320 MSPS
PDF
DAC 12 bit, 640 MSPS
PDF
Oscillators 1.0 MHz
PDF
49.152 MHz
PDF
PDF
PDF
PDF
Regulators 3.3V to 1.8V 350mA
PDF
1.8V to 0.8V 100mA
PDF
1.8V to 1.2V 200mA / 500 mA
PDF
1.8V to 0.9V 45mA / 250 mA
PDF
1.35V to 0.85V 220mA LDO
1.2V to 0.8V 550mA
PDF
POR 0.75V Power On Reset
0.8V Power On Reset
PDF
1.0 V Power on Reset
ABBG Adaptive Body Bias Generator
Detectors Droop
Low Voltage, 1.8V / 3.3V
PDF
Temperature Sensors -40 to 125°C, Resolution: 0.0625°C
PDF
-40 to 125°C, Resolution: 1°C
PVT Sensors Process, Voltage and Temperature sensor. RVT (Regular
Vt ) / LVT (Low Vt) process sensor type, 0 to 1.3V, -40 to
125°C, Resolution: 0.0625°C
PDF
Audio Codecs 24-Bit 48KHz
PDF

Contact Silvaco if you need additional info on a specific IP or you do not see the IP product you require.

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Customers

Rick Lazansky
 Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem. 
Srinath Anantharaman
 The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs. 
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