エントリー - Erick Castellon

Silvaco Exhibits and Presents Invited Paper on Atomistic Simulation at IEDM 2019

11月 19, 2019 カテゴリ: /作成者:

The IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. It is the flagship conference for

Nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices
Novel quantum and nano-scale devices and phenomenology
Optoelectronics, devices for power and energy harvesting, high-speed devices
Process technology and device modeling and simulation

Next Generation CMOS Nanowire: From Atoms to Circuit Simulation

9月 5, 2019 カテゴリ: /作成者:

Abstract— A complete simulation flow for a Nanowire-based ring oscillator circuit is presented, where the active devices were simulated using an atomistic device simulator. The results of this simulation have been fitted to an active device SPICE compact model, specifically formulated for nanowire/Gate all around Field Effect Transistors” (FETs). Finally, the active devices were incorporated into a SPICE netlist including back end resistance and capacitance parasitics.

Optimization of Select Gate Transistor in Advanced 3D NAND Memory Cell

9月 4, 2019 カテゴリ: /作成者:

Abstract—There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problems and it needs to provide enough current during read and erase operation. In this paper, we examined the design optimization of select gate transistor with respect to various device elements including work-function, S/D overlap, and trap density. Finally, we reviewed the path to reduce the channel length of the select gate transistor in conjunction with the role of dummy cells.

Estimation of Interface Property Changes Between Normally On/Off Hydrogenated Diamond MISFETs

9月 3, 2019 カテゴリ: /作成者:

Introduction
Diamond is considered to be the ultimate semiconductor material for high power and high frequency devices due to its superior electrical and thermal properties, such as high breakdown field, high carrier mobility, low dielectric constant, and high thermal conductivity, as shown in Table 1.

Furthermore, diamond has some unique electronic properties. The surface of diamond films terminated by hydrogen atoms has negative electron affinity (NEA) and can generate a two-dimensional hole accumulation layer suitable as a hole channel of a field-effect transistor.

TCAD Simulation of Electric Field Distribution in Gallium Nitride Trench-based Power Devices

7月 5, 2019 カテゴリ: /作成者:

Introduction

Gallium nitride (GaN)-based devices are excellent candidates for high-voltage and high-power applications, due to the superior physical properties of GaN compared to Si, SiC, and GaAs. Recently, GaN vertical devices have attracted increased attention, due to their advantages over GaN lateral devices, including high breakdown voltage (BV) and current capability for a given chip size, and superior thermal performance.1 Recent demonstrations of high-performance vertical GaN diodes2–4 and transistors5–9 have made vertical structures very promising for GaN power devices.