エントリー - Erick Castellon
新しいMIPI Alliance I3C V1.1標準規格とは？
I3Cは、従来のI2Cインタフェースと一定の互換性を保ちながら、ピン数削減、パフォーマンス強化、消費電力を低減する利点を持っています。2020年1月に発表された新標準規格であるI3C V1.1は、さらに高速な最大100 Mhzのインタフェース速度を実現し、他にもI2CからI3Cへの移行を支援する多くの新機能を持っています。
Victory Atomisticによる革新的ナノデバイスのTCADシミュレーション
本ウェビナーでは、シルバコのTCADツール・スイート群の一つであるVictory Atomistic (VA) のシミュレーション機能を紹介します。
Atomistic Analysis and Next Generation Computing at IEDM 2019
IEDM is THE device conference with more than a thousand participants from major companies and R&D institutes. Many talks were dedicated to new memory devices and circuits, including Ferroelectrics, MRAM, RRAM, driven by the requirements of AI processing. EUV is definitely there for 3nm and beyond. 3D integration was shown for LP-HP logic and RF. Gate-All-Around devices, with nanowires or nanosheets are mature versus FinFET.
TCAD Recommended Textbooks
CMOS: Mixed-Signal Circuit Design, Second Edition R. Jacob Baker. Published Wiley-IEEE Press, 2nd Edition. Pub […]
安全な自動運転のためのIPソリューション
本ウェビナーでは、自動車のサイバー・フィジカル・システム (Cyber-Physical System) のリスクについて、そしてシステムを保護するために必要な対策について説明します。
Customer Case Study: Using SmartSpice to Deliver Next-Generation, Low Power Memory Systems
At our SURGE Santa Clara event in October, Cameron Fisher, CEO of Mobile Semiconductor described their experience in adopting SmartSpice as their characterization engine for creating the database for their Trailblaze™ memory compiler software. Below is a summary of his talk.
Silvaco Exhibits and Presents Invited Paper on Atomistic Simulation at IEDM 2019
The IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. It is the flagship conference for
Nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices
Novel quantum and nano-scale devices and phenomenology
Optoelectronics, devices for power and energy harvesting, high-speed devices
Process technology and device modeling and simulation
AIおよびマシン･ラーニングのSoC – メモリおよびインターコネクトIPの視点
本ウェビナーでは、人工知能 (AI) およびマシン・ラーニング (ML) のSoCを開発する上での課題について考察します。
Next Generation CMOS Nanowire: From Atoms to Circuit Simulation
Abstract— A complete simulation flow for a Nanowire-based ring oscillator circuit is presented, where the active devices were simulated using an atomistic device simulator. The results of this simulation have been fitted to an active device SPICE compact model, specifically formulated for nanowire/Gate all around Field Effect Transistors” (FETs). Finally, the active devices were incorporated into a SPICE netlist including back end resistance and capacitance parasitics.