RFSOI Switch Harmonics Simulations with Trap-Rich Substrate


The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna switches which are compatible with multimode GSM/EDGE, TD/WCDMA, and LTE systems exhibit higher integration levels and have become the fastest growing mobile phone submarket.

CMOS-SOI processes, especially with thin silicon, have the potential to rival the FoM that was traditionally feasible only with GaAs technologies. This necessitates some trade-offs and optimizations of FET and substrate that need to be considered when developing a high-performance switch with high linearity and Ron*Coff < 100fs. The nonlinearity of the RF switch coming from the substrate and the active devices in terms of harmonics and intermodulation distortion could be minimized by advanced substrate and device process engineering.

Advanced material engineering has been used to suppress the substrate contribution to the harmonics and intermodulation distortion. In the domain of SOI technology, it is well established that introducing a trap-rich layer compatible with both the industrial SOI wafer production and with the thermal budget of standard CMOS process at the Si/SiO2 interface is one of the most efficient techniques to overcome the problem of the substrate’s effective resistivity degradation. This degradation is due to the formation of a parasitic surface conduction (PSC) region beneath the BOX because of fixed oxide charges (Qox) within it. The trap-rich layer aims at capturing the free carriers forming the PSC and thus allowing the substrate to retain its high nominal resistivity, leading to lower losses as well as improved linearity [1-2].

In this paper, in order to understand trap-rich substrate behavior, passive and active device on SOI with trap-rich layer structures were simulated using the Victory Device simulator. Harmonics distortion of devices were also compared.