エントリー - Erick Castellon

Remote ALTER processing

1月 1, 2004カテゴリ: /作成者:

A new parallelization method has been implemented into SmartSpice. Now .ALTERs can be destributed not only over several CPUs (by using -P option), but over a network of computers as well.

Remote .ALTER processing works the following way:

When it is invoked (by using -remote command line option), SmartSpice will read the input deck and check for .ALTER statements in it. If there are no .ALTER statements in the input deck, SmartSpice will just continue simulating the given netlist in batch mode. If .ALTERs are found, SmartSpice will extract parts of the netlist which form entire circuits and write out each circuit as separate files (.ALTER files). Resulting files containing one altered circuit each are named by adding the suffix -n to the composite basical netlist file name and have no extension. Number of produced files equals to the amount of .ALTER statements in the composite netlist plus one (deck without .ALTERs).

New SmartLIb Library of Models

1月 1, 2004カテゴリ: /作成者:

In all previous versions of SmartSpice the model code (BSIM, diode etc.) was included in the one executable (SmartSpice ). This means any updates to the model code would take a while to reach the customer because of the full SPICE functionality checks required before releasing a new SmartSpice version.

Stress Effect Model in BSIM3v3 Model

1月 1, 2004カテゴリ: /作成者:

Stress effect models are now implemented in major models such as BSIM4 or HiSIM. The need for evermore accurate models with a strong relation to technology is accute. Since BSIM3v3 is still a widely-used model and has not been totally replaced by its successor, an improvement was made to the model in SmartSpice to fulfill customers need for stress effect equations.

Sometimes I have problem to skip cells when importing cells

12月 4, 2003カテゴリ: /作成者:

Q: Sometimes I have problem to skip cells when importing cells with the same names from reference library. Once we skip one cell, expert will complain other cells already exist in the new library.

A: To process name collisions for several cells when you try to skip some of them:

1. click ‘All Existing’ button in Cell Name Collision dialog. The name of all existing cells become highlighted in grey.

Guardian DRC vs. Other DRC Systems, I

12月 1, 2003カテゴリ: /作成者:

1. Introduction

This article begins a series of articles that describe the compatibility of Guardian DRC system[1] in terms of functionality: command set, syntax and implementation with other leading industrial DRC systems. The purpose of this series is to facilitate the usage of Guardian DRC system by the designers who are already familiar with some other DRC systems.

Schematic Driven Layout

12月 1, 2003カテゴリ: /作成者:

Expert schematic driven layout (SDL) is a CAD tool which increases the productivity of layout design by automating cell generation and providing visual cues to assist the wiring process. In the current implementation, schematic driven layout is used to automatically create IC layouts based on information from a netlist. Cell instances are created from existing cells.

Interactive P-cell Generation

12月 1, 2003カテゴリ: /作成者:

1. Abstract

Parameterized cells (P-cells) significantly increase the productivity of layout designers. Silvaco International’s tool Expert has been designed to aid layout designers through its ability to support and manipulate P-cells based on its LISA script language. This simulation standard will demonstrate the capability of Expert and will identify its inherent benefits to the layout engineer.

Interconnect Parasitic Accuracy & Speed Improvements in New CLEVER Release

11月 4, 2003カテゴリ: /作成者:

Introduction

This article introduces the new features and numerical schema implemented in the most recent release of Clever from Silvaco. In this new release, both memory handling and simulation time are optimized to allow the input of larger simulation structures. In addition, the release offers greater control over the accuracy benchmarks necessary for extracted parasitic elements.