Unraveling and Optimizing Transistor-Level Simulation
Circuit Simulation is one of the most critical parts of the design process. Validating circuit behavior is essential to saving cost, minimize turn-around times and establishing reliable system characteristics before IC manufacture. To maximize throughput and efficiency, it is necessary to understand the internal methodologies and processes happening inside SPICE simulations. In this webinar, we will be presenting an in-depth understanding of the core of the SmartSpice simulator, including parallel and FastSPICE analysis modes.
After the webinar, attendees will be able to optimize the performance of SmartSpice and SmartSpice Pro in accordance with their design applications and methodology to achieve the ideal balance of Accuracy-of-analysis versus Speed-of-analysis.
What attendees will learn:
- Simulation Process and Framework
- Convergence
- Numerical Integration
- Timestep Control
- FastSPICE Simulation Technology
- Trading off Accuracy versus Speed
Presenter
Robert Villanueva is an Applications Engineer within the Front-End EDA Division working on numerous simulation technologies and responsible for Silvaco’s FastSPICE Simulator worldwide support. He is active in the Si2-Compact Model Coalition and HiSIM Consortium – SPICE Model Standardization Groups. With more than 15 years in the IC design and EDA industry, he is well experienced in CMOS circuit designs, empirical models, and various major commercial circuit simulators.
Mr. Villanueva holds a Bachelor and a Master’s Degree in Electronics and Communications Engineering from Saint Louis University Philippines (Cum Laude). He is a duly licensed Electronics and Communications Engineer by the Philippine Professional Regulation Commission.
When: April 25, 2019
Where: Online
Time: 10:00am-11:00am – (PST)
Language: English
WHO SHOULD ATTEND:
Analog Circuit Designers, CAD Engineers in the Circuit Simulation Field, Engineers and Students new to Circuit Simulation.