How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
Memory Layout
Silvaco embedded memories are ideal for ultra-low power, high-density applications and have been in production use for the past 25 years. The SRAMs, Register Files, and ROMs targeting more than 12 foundries and IDM’s, are available in multiple generations of nodes and different processes and have resulted in successful silicon for thousands of designs and millions of manufactured wafers.
This webinar presents Silvaco’s Embedded Memory offerings as part of a complete Foundation IP suite that includes Standard Cells and IO’s. You will learn about
· Silvaco memory technology for SRAMs, Register Files, and ROMs
· Overview of the unique architecture enabling high densities and low power
· Application of Silvaco’s embedded memories in various applications
Presenter
Eitan Zmora, Memory Architect, Silvaco
Eitan Zmora is a Memory Architect and held the same role, prior to Silvaco, at Dolphin Design. He is a designer of multiple embedded memory architectures including Single Port SRAM, 1 Port Register File, Dual Port SRAM, and 2 Port Register File. As a chip design engineer and technical manager, he has more than 25 years of experience in VLSI circuit design and Foundation IP development.
WHO SHOULD ATTEND:
IC architects, managers, and circuit designers.
When: February 23, 2021
Where: Online
Time: 10:00am-10:30am-(PST)
Language: English