Jivaro Runtime Reduction

Utmost IV를 이용하여 TFT 및 OLED에 대해 SPICE 모델링

2020년 5월 15일 | 2:00am-2:300am (한국 시각) 실바코의 Utmost IV 모델링 소프트웨어를 사용하여 FPD 애플리케이션과 관련된 SPICE 모델링 접근 방식 및 방법에 대해 알아봅니다. 주파수 분산 효과와 같은 문제를 중심으로, TFT 소자 모델링, Verilog-A 모델 및 매크로모델 사용 등 OLED 소자의 모델링 등을 논의할 것입니다.
Jivaro Runtime Reduction

Utmost IV Quick-Start 모델 최적화 템플릿

2020년 3월 13일 | 2:00am-2:30am (한국 시각) UTMOST IV: Quick-Start Optimization Templates에서 사용할 수 있는 새로운 기능을 소개합니다. 이 기능은 사용자가 데이터를 기반으로 특정 모델에 대한 최적화 프로젝트를 신속하게 생성할 수 있는 기능입니다. 따라서 SPICE 모델링 경험이 거의 없더라도, 사용자의 생산성을 크게 향상시킬 수 있습니다.
Jivaro Runtime Reduction

Jivaro 기생성분 추출로 회로 시뮬레이션의 시간 단축 실현

2020년 1월 17일 | 3:00am-3:30am - (한국 시각) Jivaro에 대한 간략한 소개 후, 더 나은 넷리스트 감소를 위해 필요한 기능과 제어 기법을 제시하여 시뮬레이션 흐름을 개선하기 위한 방법론을 살펴봅니다.
Jivaro Runtime Reduction

기생성분 감축

Jivaro Parasitic Reduction for Fast, Accurate Simulation Jivaro is a unique stand-alone solution dedicated to the reduction of parasitic networks. It helps back-end verification teams speed up post-layout SPICE simulation of huge extracted parasitic circuits, while keeping high accuracy.

회로 시뮬레이션

SmartSpice Circuit SimulatorSilvaco’s SmartSpice™ is a high performance parallel SPICE simulator that delivers industry leading accuracy. It is a proven, comprehensive solution for applications including simulation of complex high precision analog and mixed-signal circuits, memory, custom digital design and characterizing cell libraries of advanced semiconductor processes.
Jivaro Runtime Reduction

공정 변동 및 수율 분석

Jivaro Runtime Reduction

기생성분 감축 및 분석

Jivaro is a unique stand-alone solution dedicated to the reduction of parasitic networks. It helps back-end verification teams speed up post-layout SPICE simulation of huge extracted parasitic circuits, while keeping high accuracy.Viso analyzes the electrical properties of RC parasitic networks which crucially impact circuit behavior in nanometer processes. These impacts affect circuit gain, delay, maximum clock rate, cross-coupling, level of ESD protection and other features, which can cripple a design. Viso’s parasitics-focused approach enables quick analysis of interconnect in order to pinpoint problems. It provides timing estimation and accurate comparison of different extracted netlists.Belledonne is used for layout comparison via extracted netlist. It compares two different extracted netlists and is mainly used for layout parasitic extraction (LPE) flow qualification.
Jivaro Runtime Reduction

아날로그 시뮬레이션

Silvaco’s SmartSpice is a high performance parallel SPICE simulator that delivers industry leading accuracy. It is a proven, comprehensive solution for applications including simulation of complex high precision analog and mixed-signal circuits, memory, custom digital design and characterizing cell libraries of advanced semiconductor processes. It uses an intelligent architecture deploying multiple solvers, stepping algorithms and computation techniques. The result is accurate, robust convergence and industry leading performance and capacity – over 8 million active devices. It is compatible with HSPICE® and Spectre® for netlists, models, analysis features, and results – plus large libraries of calibrated device models are available. Featuring integration with Silvaco Gateway schematic editor and SmartView waveform viewer, SmartSpice fits seamlessly into front-end analog IC design flows.
Jivaro Runtime Reduction

SPICE 모델 생성