Victory Atomistic TCAD 솔루션을 통해 나노 크기 원자 소자의 프로토타입 구현
2022년 9월 9일 | 2:00am-2:30am (한국 시각)
이번 시간에, 초고밀도 전계효과 트랜지스터(FET) 기술에서 5nm 노드 이하의 최신 기술 아키텍처를 설계하기 위해 원자 규모 시뮬레이션이 필요하다는 점을 설명합니다. Victory Atomistic 솔루션을 상세히 살펴봅니다.
저자는 아직 경력을 작성하지 않았습니다.
하지만, Gigi Boss 씨는 무려 351 항목에 기여한 것을 자랑스럽게 생각합니다.
2022년 9월 9일 | 2:00am-2:30am (한국 시각)
이번 시간에, 초고밀도 전계효과 트랜지스터(FET) 기술에서 5nm 노드 이하의 최신 기술 아키텍처를 설계하기 위해 원자 규모 시뮬레이션이 필요하다는 점을 설명합니다. Victory Atomistic 솔루션을 상세히 살펴봅니다.
New Features in the 2022 Baseline Release:
2022년 8월 12일 | 2:00am-2:30am (한국 시각)
이번 시간에, FinFET 및 메모리 애플리케이션에서의 기하학적 식각 모델을 제시합니다. 핀의 형성, 비이상적 식각 프로파일 (휘어짐, 비틀림), 자체 정렬 공정 (멀티 패터닝)을 실현하는 기술을 설명합니다.
This work reports on the design of a high efficiency InGaN-based two junction (2J) tandem solar cell via numerical simulation, operating at high temperatures (450o C) and under 200 suns for application in a hybrid concentrating solar thermal (CST) system. To address the polarization and band-offset issues for GaN/InGaN heterojunction solar cells, band engineering techniques are employed. A simple interlayer is proposed at the hetero-interface rather than using an In composition grading layer, which is difficult to fabricate. The base absorber thickness and doping concentration have been optimized for 1J cell performance, and current matching was imposed on the series constrained 2J tandem cell design. The simulation results show that the crystalline quality (short recombination lifetime) of current nitride materials is a critical limiting factor the performance of the 2J cell design at high temperatures. The theoretical conversion efficiency of the best devices can be as high as ~21.8% at 450o C and 200X based on the assumed material parameters.
2022년 7월 1일 | 2:00am-2:30am (한국 시각)
이번 시간에 스키매틱와 레이아웃 편집, 최신 TFT 기술에 요구되는 정확한 필드 솔버 기반 기생 추출, 기생 RC 요소의 넷리스트에 대한 백 애노테이션, 대규모 픽셀 어레이의 빠르고 정확한 SPICE 시뮬레이션을 위해 주요 디스플레이 및 검출기 기업이 실바코 툴을 어떻게 활용하고 있는지 설명합니다.
2022년 6월 10일 | 2:00am-2:30am (한국 시각)
이번 시간에 디스플레이 업계의 고질적인 문제인 화면 잔상에 대한 솔루션과 SPICE 수준에서 시뮬레이션하는 방법을 소개합니다.
Self-heating effect may cause over-heated damage and degradation for silicon-on-insulator (SOI) devices, so numerical counting heat generated, and distribution can optimize the radio frequency integrated circuits (RFICs) applications. Both conventional and high resistivity, trap-rich SOI substrates are fabricated to investigate self-heating effects. There are two identical n channel metal-oxide-semiconductor-field-effect transistors (nMOSFETs) placed together to share a common source and the same active silicon region. One MOSFET is biased above threshold voltage and into saturation to heat-up the active region as a heater, and another device is biased into the sub-threshold regime to track the temperature changes as a localized thermometer. Compared to bulk single crystal silicon, the trap-rich SOI substrate consists of a high-defected polysilicon layer, which has introduced between the buried oxide layer and substrate. Due to the grain boundaries, the polysilicon layer has more phonon scattering and less value of thermal conductivity. However, based on the measurement results, two types of substrates SOI devices have similar performance for temperature increased. Therefore, a Silvaco numerical simulation has been issued to analysis the heat flow distribution within the devices and dissipation solution.
2022년 5월 13일 | 2:00am-2:30am (한국 시각)
이번 시간에 실바코가 제공하는 AMBA AHB 서브시스템과 제품에 대해 간략하게 소개합니다. 논의 주제에 채널 대 패브릭 아키텍처, 저전력, 커스터마이징, 하드웨어 및 소프트웨어 기반 보안, 하드웨어 및 소프트웨어에 대한 공동 검증을 포함합니다.
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