It is common to run the process simulation for the part of a larger structure just to reduce the computation time. To account for the influence of parts of the structure outside the simulation domain, Victory Process makes assumptions about overall structure geometry.

The utilization of thin material layers is common in modern semiconductor device fabrication. Subsequent etching steps require an accurate modeling of these thin layers. Although level-set based process TCAD simulations are capable of representing flat thin material layers with sub-grid accuracy, topographical changes during etching processes expose the low underlying grid resolution, which leads to detrimental artifacts.