CMOS Technology

The full text for most of these papers may be found at the IEEE website at www.ieee.org.

T Uchino^{1, 2,} E Gili^{1, 3,} L Tan^4, O Buiu^4, S Hall⁴ and P Ashburn¹,
“Improved vertical MOSFET performance using an epitaxial channel and a stacked silicon-insulator structure”

School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK
Department of Electronics and Intelligent Systems, Tohoku Institute of Technology, Sendai, 982-8577, Japan
Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE, UK
Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, L69 3GJ, UK

B. Grandchamp, M.-A. Jaud, P. Scheiblin, K. Romanjek, L. Hutin, C. Le Royer, M. Vinet,
“In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation”,
Solid-State Electronics, Vol. 57, Issue 1, March 2011, pp. 67–72.

Chi-Woo Lee, Isabelle Ferain, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, Jean-Pierre Colinge,
“Performance estimation of junctionless multigate transistors”,
Solid-State Electronics, Vol. 54, Issue 2, February 2010, pp. 97-103.

V. Vasireddy, S. Parke,
“Simulation and Experimental Results of a 0.15µm Independent Double Gated CMOS Transistor”,
2010 18th Biennial University/Government/Industry Micro/Nano Symposium (UGIM), 2010, pp. 1&3.

F. Salehuddin, I. Ahmad, F.A Hamid, A. Zaharim,
“Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method”,
2010 IEEE International Conference on Semiconductor Electronics (ICSE), 2010, pp. 19&24.

A. Abdul Aziz, S. S. Osman,
“A Simulation based study on C-V characteristics of oxide thickness for NMOS”,
2010 Intl Conf on Electronic Devices, Systems and Applications (ICEDSA), 2010, pp. 404&407.

Sarvesh Dubey, Pramod Kumar Tiwari, S. Jit,
“A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical Gaussian-like doping profile”,
Journal of Applied Physics, Vol. 108 , Issue: 3, 2010, pp. 034518&034518-7.

P. Rakesh Kumar, Santanu Mahapatra,
“Analytical modeling of quantum threshold voltage for triple gate MOSFET”,
Solid-State Electronics, Vol. 54, Issue 12, December 2010, pp. 1586-1591.

A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, G. Pananakakis, N. Collaert,
“Analytical modelling for the current–voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs”,
Microelectronic Engineering, Vol. 87, Issue 9, November 2010, pp. 1764-1768.

M. Cheralathan, A. Cerdeira, B. Iñiguez,
“Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations”,
Solid-State Electronics, In Press, Corrected Proof, Available online 23 September 2010.

M. Najmzadeh, K. Boucart, W. Riess, A.M. Ionescu,
“Asymmetrically strained all-silicon multi-gate n-Tunnel FETs”,
Solid-State Electronics, Vol. 54, Issue 9, September 2010, pp. 935-941.

Munawar A. Riyadi, Ismail Saad, Razali Ismail,
“Investigation of pillar thickness variation effect on oblique rotating implantation (ORI)-based vertical double gate MOSFET”,
Microelectronics Journal, In Press, Corrected Proof, Available online 22 July 2010.

U. Monga, H. Børli, T. A. Fjeldly,
“Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs”,
Mathematical and Computer Modelling, Vol. 51, Issues 7-8, April 2010, pp. 901-907.

K. Park, P. Nayak, D.K. Schroder,
“Role of the substrate during pseudo-MOSFET drain current transients”,
Solid-State Electronics, Vol. 54, Issue 3, March 2010, pp. 316-322.

Woo Young Choi,
“Applications of impact-ionization metal–oxide-semiconductor (I-MOS) devices to circuit design”,
Current Applied Physics, Vol. 10, Issue 2, March 2010, pp. 444-451.

K. Romanjek, E. Augendre, W. Van Den Daele, B. Grandchamp, L. Sanchez, C. Le Royer, J.-M. Hartmann, B. Ghyselen, E. Guiot, K. Bourdelle, S. Cristoloveanu, F. Boulanger, L. Clavelier,
“Improved GeOI substrates for pMOSFET off-state leakage control Microelectronic Engineering”,
In Press, Corrected Proof, Available online 16 March 2009.

Ravneet Kaur, Rishu Chaujar, Manoj Saxena, R. S. Gupta,
“cwith gate stack configuration”,
Microelectronic Engineering, In Press, Corrected Proof, Available online 17 January 2009.

P. Martin, M. Cavelier, R. Fascio, G. Ghibaudo, M. Bucher,
“EKV3 compact modeling of MOS transistors from a 0.18 μm CMOS technology for mixed analog–digital circuit design at low temperature Cryogenics”,
In Press, Corrected Proof, Available online 1 January 2009.

Ravneet Kaur, Rishu Chaujar, Manoj Saxena, R.S. Gupta,
“Two dimensional simulation and analytical modeling of a novel ISE MOSFET with gate stack configuration”,
Microelectronic Engineering, Vol. 86, Issue 10, October 2009, pp. 2005-2014.

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R.S. Gupta,
“TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation”,
Superlattices and Microstructures, Vol. 46, Issue 4, October 2009, pp. 645-655.

Xi Liu, Xiaoshi Jin, Jong-Ho Lee,
“A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs”,
Solid-State Electronics, Vol. 53, Issue 9, September 2009, pp. 1041-1045.

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta,
“TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation”,
Superlattices and Microstructures, Vol. 46, Issue 4, October 2009, pp. 645-655.

B. Ayub, M. Rusop,
“The effect of gate dielectric thickness on PMOS performance”,
AIP Conference Proceedings, Vol. 1136, 2009, pp. 560-564.

O. Suziana, B. Ayub, M. Redzuan, A. R. Shahrir, M. Y. Yunus, M. H. Abdullah, U. M. Noor, M. Rusop,
“Effect of doping concentration on electrical characteristics of NMOS structure”,
AIP Conference Proceedings, Vol. 1136, 2009, pp. 575-580.

M. Redzuan, B. Ayub, M. Shahrir, O. Suziana, M. Yunus, M. H. Abdullah, U. M. Noor, M. Rusop,
“Mesh grid of SILVACO TCAD effect on net doping profile for NMOS structures”,
AIP Conference Proceedings, Vol. 1136, 2009, pp. 581-585.

A. R. Shahrir, M. Rusop,
“The threshold voltage properties of NMOS structure etched with different etching methods”,
AIP Conference Proceedings, Vol. 1136, 2009, pp. 555-559.

Woo Young Choi,
“Applications of impact-ionization metal-oxide-semiconductor (I-MOS) devices to circuit design”,
Current Applied Physics, In Press, Corrected Proof, Available online 3 July 2009.

Chang-Hoon Kim¹, Cheulhee Jung², Hyun Gyu Park² & Yang-Kyu Choi¹
“Novel Dielectric-Modulated Field-Effect Transistor for Label-Free DNA Detection”

Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Republic of Korea
Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Republic of Korea
Biochip Journal, Vol. 2, No. 2, 127-134, June 2008

Ratul Kumar Baruah, Santanu Mahapatra,
“Justifying threshold voltage definition for undoped body transistors through “crossover point” concept”,
Physica B: Condensed Matter, Vol. 404, Issues 8-11, 1 May 2009, pp. 1029-1032.

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta,
“Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI”,
Microelectronic Engineering, Vol. 85, Issue 3, March 2008, pp. 566-576.

Lizhe Tan, Octavian Buiu, Stephen Hall, Enrico Gili, Takashi Uchino, Peter Ashburn,
“The influence of junction depth on short channel effects in vertical sidewall MOSFETs”,
Solid-State Electronics, Vol. 52, Issue 7, July 2008, pp. 1002-1007.

F. Lime, B. Iniguez, O. Moldovan,
“A quasi-two-dimensional compact drain-current model for undoped symmetric double-gate MOSFETs including short-channel effects”,
IEEE Transactions on Electron Devices, Vol. 55, No. 6, June 2008, pp. 1441-1448.

S. Capraro¹, C. Bermond¹, T.T. Vo¹, J. Piquet¹, B. Fléchet¹, M. Thomas², A. Farcy², J. Torres², S. Cremer2, E. Guichard³, A. Haen³,
” “Design Improvement of RF 3D MIM Damascene Capacitor “”

LAHC, IMEP-LAHC, Université de Savoie, Campus Scientifique, 73736 Le Bourget du Lac, France
STMicroelectronics, 850 rue J. Monnet, 38926 Crolles cedex, France
Silvaco Data Sytems, 55 rue Pascal Blaise, 38330 Montbonnot St Martin, France

Yu. P. Snitovsky, M. G. Krasikov,
“New CMOS process using a thermal-oxide mask for making n^– – and p^– – wells”,
Russian Microelectronics, Vol. 37, No. 3, May 2008, pp. 166-174.

A. S. Zoolfakar, H. Hashim,
“Comparison between Experiment and Process Simulation Results for Converting Enhancement to Depletion Mode NMOS Transistor”,
Second Asia International Conference on Modeling & Simulation,
2008. AICMS 08. 13-15 May 2008 pp. 1061&1064.

S. F. W. M. Hatta, N. Soin,
“Design of a low voltage CMOS LNA at 2 GHz with substrate-bias”,
AIP Conference Proceedings, Vol. 1060, 2008, pp. 244-249

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R.S. Gupta,
“Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI”,
Microelectronic Engineering, Vol. 85, Issue 3, Mar. 2008, pp. 566-576.

Zoolfakar A. S., Hashim H.,
“Comparison between Experiment and Process Simulation Results for Converting Enhancement to Depletion Mode NMOS Transistor”,
Second Asia International Conference on Modeling & Simulation, AICMS 2008. 13-15 May 2008, pp. 1061-1064.

Harsupreet Kaur, Sneha Kabra, Subhasis Haldar and R.S. Gupta,
“An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET”,
Microelectronics Journal, Vol. 38, Issue 3, March 2007, pp. 352-359.

Kathy Boucart and Adrian Mihai Ionescu,
“Double-Gate Tunnel FET With High- k Gate”
IEEE Transactions on Electron Devices, VOL 54, NO 7, July 2007

F. Mayer, C. Le Royer, G. Le Carval, C. Tabone, L. Clavelier and S. Deleonibus,
“Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS)”,
Solid-State Electronics, Vol. 51, Issue 4, April 2007, pp. 579-584.

X. Loussier, D. Munteanu and J. L. Autran,
“Impact of high-permittivity dielectrics on speed performances and power consumption in double-gate-based CMOS circuits”,
Journal of Non-Crystalline Solids, Vol. 353, Issues 5-7, 1 April 2007, pp. 639-644.

Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park,
“Design and simulation of asymmetric MOSFETs “,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-C, No. 5, May 2007, p 978-982.

Ulrich Abelein, Andreas Assmuth, Peter Iskra, Markus Schindler, Torsten Sulima and Ignaz Eisele,
“Doping profile dependence of the vertical impact ionization MOSFET´s (I-MOS) performance”,
Solid-State Electronics, Vol. 51, Issue 10, October 2007, pp. 1405-1411.

Jong Pil Kim (Seoul Nat. Univ., Seoul, South Korea), Woo Young Choi, Jae Young Song, Sang Wan Kim, Jong Duk Lee; Byung-Gook Park,
“Design and fabrication of asymmetric MOSFETs using a novel self-aligned structure”,
IEEE Transactions on Electron Devices, Vol. 54, No. 11, Nov. 2007, pp. 2969-2974.

P. K. Ooi, K. Ibrahim,
“Simulation of single channel length vertical silicon MOSFET”,
AIP Conference Proceedings, Vol. 1017, 2007, pp. 154-158.

S. Michael, L.T.B. Canfield,
“The design and optimization of advanced thermophotovoltaic devices for deep space applications using a new modeling approach”,
AIP Conference Proceedings, Vol. 890, No. 1, 2007, pp.s 213-226.

G. M. Buiatti, F. Cappelluti, G. Ghione,
“Physics-based PiN diode SPICE model for power-circuit simulation”,
IEEE Transactions on Industry Applications, Vol. 43, No. 4, July-August 2007, pp. 911-919.

I. V. Kotova, T. J. Humanica, D. Nouaisb, J. Randela, A. Rashevskyc,
“Electric fields in nonhomogeneously doped silicon. Summary of simulations”
Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 568 (1), pp. 41-45, July 10 2006.

M. Elgin, D. Russell, M. Katula, R. Paulsen, S. Parke,
“CMOS imager pixel design for space applications”,
Microelectronics and Electron Devices, 2006. WMED ’06. 2006 IEEE Workshop on 14 April 2006, pp. 1.

Vaskar Sarkara and Aloke K. Dutta,
“An accurate, analytical, and technology-mapped definition of the surface potential at threshold and a new postulate for the threshold voltage of MOSFETs”
Solid-State Electronics Vol. 50, Issues 11-12, November-December 2006, pp. 1814-1821.

M. Masahara, Y. Liu, K. Ishii, K. Sakamoto, T. Matsukawa, H. Tanoue, S. Kanemaru, E. Suzuki,
“Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors”
Applied Physics Letters, Vol. 86, Issue 12, 21 March 2005, pp. 1-3.

K. K. Bhuwalka, J. Schulze, I. Eisele,
“Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering”
IEEE Transactions on Electron Devices Vol. 52, Issue 5, May 2005, pp. 909-917.

K. Chong, X. Zhang, K.-N. Tu, D. Huang, M.-C. Chang, Y.-H. Xie,
“Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC)”
IEEE Transactions on Electron Devices, Vol. 52, Issue 11, November 2005, pp. 2440-2446.

P. Kasturi, M. Saxena, R. S. Gupta,
“Modeling and simulation of STacked Gate Oxide (STGO) architecture in Silicon-On-Nothing (SON) MOSFET”
Solid-State Electronics, Vol. 49, Issue 10, October 2005, pp. 1639-1648.

M. De Souza, M. A. Pavanello, B. Iniguez, D. Flandre,
“A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation”
Solid-State Electronics, Vol. 49, Issue 10, October 2005, pp. 1683-1692.

G. Nicholas, T. J. Grasby, E. H. C. Parker, T. E. Whall, T. Skotnicki,
“Evidence of reduced self-heating in strained Si MOSFETs”
IEEE Electron Device Letters, Vol. 26, Issue 9, September 2005, pp. 684-686.

M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, E. Suzuki,
“Demonstration, analysis, and device design considerations for independent DG MOSFETs”
IEEE Transactions on Electron Devices, Vol. 52, Issue 9, September 2005, pp. 2046-2053.

G. Curatola, G. Doornbos, J. Loo, Y. V. Ponomarev, G. Iannaccone,
“Detailed modeling of sub- 100-nm MOSFETs based on Schrodinger DD per subband and experiments and evaluation of the performance gap to ballistic transport”
IEEE Transactions on Electron Devices, Vol. 52, Issue 8, August 2005, pp. 1851-1858.

D. Munteanu, J. L. Autran, S. Harrison,
“Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics”
Journal of Non-Crystalline Solids, Vol. 351, Issue 21-23, 15 July 2005, pp. 1911-1918.

V. D’Alessandro, P. Spirito,
“Achieving accuracy in modeling the temperature coefficient of threshold voltage in MOS transistors with uniform and horizontally nonuniform channel doping”
Solid-State Electronics, Vol. 49, Issue 7, July 2005, pp. 1098-1106.

A. R. Saha, S. Chattopadhyay, C. Bose, C. K. Maiti,
“Technology CAD of silicided Schottky barrier MOSFET for elevated source-drain engineering”
Materials Science and Engineering B: Solid-State Materials for Advanced Technology, 2005, Vol. 124-125, pp. 424-430.

J. Yuan, J. C. S. Woo,
“A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output”
IEEE Electron Device Letters, Vol. 26, Issue 11, November 2005, pp. 829-831

E. J. Preisler, S. Guha, B. R. Perkins, D. Kazazis, A., Zaslavsky,
“Ultrathin epitaxial germanium on crystalline oxide metal-oxide-semiconductor-field-effect transistors”
Applied Physics Letters, Vol. 86, Issue 22, 2005, pp. 1-3.

K. Goel, M. Saxena, M. Gupta, R. S. Gupta,
“Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET”
IEEE Transactions on Electron Devices, Vol. 52, Issue 1, January 2005, pp. 23-29.

A. Gokirmak, S. Tiwari,
“Threshold voltage tuning and suppression of edge effects in narrow channel MOSFETs using surrounding buried side-gate”
Electronics Letters, Vol. 41, Issue 3, 3 February 2005, pp. 157-158.

I. Nam, K. Lee,
“High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology”
IEEE Journal of Solid-State Circuits, Vol. 40, Issue 2, February 2005, pp. 392-402.

A. Ohata,
“Evaluation of performance degradation factors for high-k gate dielectrics in N-channel MOSFETs”
Solid-State Electronics, Vol. 48, Feb. 2004, pp. 345&349.

S. -E. Tan,
“Velocity saturation in PMOSFET: Using different inversion layer mobility models”
10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys.

S. -E. Tan,
“Effects of normal electric field on submicrometer PMOSFET”
10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys.

Y. David and U. Efron,
“Design and analysis of an image transceiver device with a low cross-talk level”
IEEE Convention of Electrical and Electronics Engineers in Israel, Proceedings 2004, pp. 41-43.

T. Uchino, P. Ashburn, Y. Kiyota, T. Shiba,
“A CMOS-compatible rapid vapor-phase doping process for CMOS scaling”
IEEE Transactions on Electron Devices, Vol. 51, Issue 1, January 2004, pp. 14-19

H. Lee, H. Shin, J. Lee,
“Design of a 20 nm T-gate MOSFET with a Source/Drain-to-Gate Non-Overlapped Structure”
Journal of the Korean Physical Society, Vol. 44, Issue 1, January 2004, pp. 65-68.

M. -A. Jaud, S. Barraud, G. Le Carval,
“Impact of quantum mechanical tunneling on off-leakage current in double-gate MOSFET using a quantum drift-diffusion model”
2004 NSTI Nanotechnology Conference and Trade Show&NSTI Nanotech 2004 Vol. 2, 2004, pp. 17-20.

M. Masahara, Y. Liu, S. Hosokawa, T. Matsukawam K. Ishii, H. Tanoue, K. Sakomoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki,
“Ultrathin Channel Vertical DG MOSFET Fabricated by using Ion-Bombardment-Retarded Etching”
IEEE Trans, Electron Devices, Vol. 51, Dec 2004, pp. 2078-2085.

Pascal Scheiblin and Johann Foucher,
“Three-Dimensional Simulation of the Effect of E-Beam Lithography Induced Line-Edge Roughness on N-Type Metal-Oxide Semiconductor Transistor Electrical Characteristics for a 50nm Technology”
Japanese Journal of Applied Physics Vol. 43 No. 6B, 2004, pp. 3838-3842.

S. C. Kelly, J. A. Power, M. O’Neill,
“Selection and modeling of integrated RF varactors on a 0.35-μm BiCMOS technology ”
IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 2, May, 2004, The International Co.

J. Yuan and J. C. S. Woo,
“Nanoscale MOSFET with split-gate design for RF/analog application”
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 43, No. 4B, pp. 1742-1745 (2004).

E. Gili, V. D. Kunz, C. H. De Groot, T. Uchino, P. Ashburn, D. C. Donaghy, S. Hall, Y. Wang, P. L. F. Hemment,
“Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance”
Solid-State Electronics, Vol. 48, Issue 4, April 2004, pp. 511-519.

N. D. Jankovic and G. A. Armstrong,
“Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers”
Microelectronics Journal, Vol. 35, Issue 8, August 2004, pp. 647-653.

N. G. Gunther, I. I. Pesic, A. A. Mutlu, M. Rahman,
“Modeling C&V characteristics of deep sub-0.1 micron mesoscale MOS devices”
Solid-State Electronics, Vol. 48, Issue 10-11 SPEC. ISS., October 2004, pp. 1883-1890.

N. P. Hong, J. -W Hong,
“Charge storage characteristics of SiO2/Si3N 4 double layer electret”
Proceedings of the 2004 IEEE International Conference on Solid Dielectrics ICSD 2004, Vol. 1, Pro.

G. Pei, E. C. -C. Kan,
“Independently driven DG MOSFETs for mixed-signal circuits: Part I&Quasi-static and nonquasi-static channel coupling”
IEEE Transactions on Electron Devices, Vol. 51, Issue 12, December 2004, pp. 2086-2093.

G. Pei, E. C. C. Kan,
“Independently driven DG MOSFETs for mixed-signal circuits: Part II&Applications on cross-coupled feedback and harmonics generation”
IEEE Transactions on Electron Devices, Vol. 51, Issue 12, December 2004, pp. 2094-2101.

M. Masahara, Y. Liu, S. Hosokawa, T. Matsukawa, K. Ishii, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, E. Suzuki,
“Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching”
IEEE Transactions on Electron Devices, Vol. 51, Issue 12, December 2004, pp. 2078-2085.

A. Y. Kovalgin, J. Holleman, G. Iordache, T. Jenneboer, F. Falke, V. Zieren, M. Goossens,
“Low-power micro-scale CMOS-compatible silicon sensor on a suspended membrane”
Electrochemical Society Proceedings, Vol. 9, 2004, pp. 173-183.

M. Stadele, R. J. Luyken, M. Roosz, M. Specht, W. Rasner, L. Dreeskornfeld, J. Hartwich, F. Hofmann, J. Kretz, E. Landgraf, L. Risch,
“A comprehensive study of corner effects in tri-gate transistors”
ESSCIRC 2004&Proceedings of the 34th European Solid-State Device Research Conference, 2004.

F. -L. Chang, M. -J. Lin, C. W. Liaw, T. -C. Liao, H. -C. Cheng,
“Investigation of A 450 V rating silicon-on-insulator lateral-double-diffused-metal-oxide-semiconductor fabrication by 12/25/5/40 V bipolar-complementary metal-oxide-semiconductor double-diffused metal-oxide-semiconductor process on bulk silicon substrate”
Japanese Journal of Applied Physics, 2004, Vol. 43, pp. 4119-4123.

U. Efron, I. David, V. Sinelnikov, B. Apter,
“A CMOS/LCOS image transceiver chip for smart goggle applications”
IEEE Transactions on Circuits and Systems for Video Technology, Vol. 14, Issue 2, February 2004,

A. K. Sharma, S. H. Zaidi, S. Lucero, S. R. J. Brueck, N. E. Islam,
“Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs”
IEE Proceedings: Circuits, Devices and Systems, Vol. 151, Issue 5, October 2004, pp. 422-430.

M. Lemme, et al.,
“Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate”
Microelectronic Engineering, Vol. 67-68, June 2003, pp. 810-817.

T. S. Park, E. Yoon, J. H. Lee,
“A 40 nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer”
Physica E: Low-dimensional Systems and Nanostructures, Vol. 19, Jul. 2003, pp. 6 -12.

R. Granzner, V. M. Polyakov, F. Schwierz, M. Kittler, T. Doll,
“On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs”
Physica E: Low-dimensional Systems and Nanostructures, Vol. 19, Jul. 2003, pp. 33&38.

A. Mannargudi, D. Vasileska,
“Quantum confinements in highly asymmetric sub-micrometer device structures”
Superlattices and Microstructures, Vol. 34 (3-6), Sep-Dec 2003, pp. 347-354.

R. B. Beck,
“Formation of ultrathin silicon oxides-modeling and technological constraints”
Materials Science in Semiconductor Processing, Vol. 6, February-June 2003, pp. 49-57.

J. Urresti, S. Hidalgo, D. Flores, J. Roig, J. Rebollo, I. Mazarredo,
“Optimisation of very low voltage TVS protection devices”
Microelectronics Journal, Vol. 34, September 2003, pp. 809-813.

S. K. Han, Y. I. Choi and S. K. Chung,
“An analytic model for breakdown voltage of gated diodes”
Microelectronics Journal, Vol. 34, May-Aug. 2003, pp. 525-527.

Iliya Pesic, Norman Gunther, Ayhan Mutlu, and Mahmud Rahman,
“Modeling C-V Characterisitics of Deep Sub&0.1 Micron Mesoscale MOS Devices”
Proceedings of 2003 International Semiconductor Device Research Symposium, Washington DC, December 1.

A. Breed and K. P. Roenker,
“Dual-gate (FinFET) and Tri-Gate MOSFETs: Simulation and Design”
Proceedings of 2003 International Semiconductor Device Research Symposium, Washington DC, December 1.

M. Saxena, S. Haldar, M. Gupta, R. S. Gupta,
“Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET”
Solid-State Electronics, Vol. 47, November 2003, pp. 2131-2134.

T. Ivanov, T. Gotszalk, T. Sulzbach, I. W. Rangelow,
“Quantum size aspects of the piezoresistive effect in ultra thin piezoresistors”
Ultramicroscopy, Vol. 97, October-November 2003, pp. 377-384.

M. Masahara, T. Matsukawa, H. Tanoue and et al.,
“Novel process for vertical double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET) fabrication”
Jpn. J. Appl. Phys. 1, Vol. 42, Jun. 2003, pp. 4138&4141.

G. M. Laws, T. J. Thornton, J. Yanga, L. de la Garza, M. Kozicki, D. Gust, J. Gu, D. Sorid,
“Drain current control in a hybrid molecular/MOSFET device”
Physica E: Low-dimensional Systems and Nanostructures, Vol. 17, April 2003, pp. 659&663.

M. Masahara, T. Matsukawa, K. Ishii and et al.,
“Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)”
Jpn. J. Appl. Phys. 1, Vol. 42, Apr. 2003, pp. 1916&1918.

T. Ivanov, T. Gotszalk, T. Sulzbach, I. Chakarov and I. W. Rangelow,
“AFM cantilever with ultra-thin transistor-channel piezoresistor: quantum confinement”
Microelectronic Engineering, Vol. 67-68, 2003, pp. 534-541.

H. Koo, K. Lee, K. Lee, T. A. Fjeldly, M. S. Shur,
“Analysis of the anomalous drain current characteristics of halo MOSFETs”
Solid-State Electronics, Vol. 47, January 2003, pp. 99-106.

Anand Mannargudi and Dragica Vasileska,
“Monte Carlo and Energy Balance Simulations of Deep-micrometer Conventional and Asymmetric MOSFET Device Structures”
Nanotech 2003, Vol. 2, pp. 1-4.

M. Saxena, S. Haldar, M. Gupta and et al.,
“Physics-based modelling and simulation of dual material gate stack (DUMGAS) MOSFET”
Electron Letter, Vol. 39, Jan. 2003, pp. 155-157.

C. Cavallaro, S. Musumeci, R. Pagano, A. Raciti, K. Shenai,
“Analysis Modeling and Simulation of Low-Voltage MOSFETs in Synchronous-Rectifier Buck-Converter Applications”
IECON Proceedings (Industrial Electronics Conference), Vol. 2, 2003, pp. 1697-1702.

R. R. Whiteman, A. P. Knights, D. George, I. E. Day, A. Vonsovici, A. A. House, G. F. Hopper, M. Asghari,
“Recent progress in the design, simulation and fabrication of small cross-section silicon-on-insulator VOAs”
Proceedings of SPIE&The International Society for Optical Engineering, Vol. 4997, 2003, pp. 1.

Sheehan, D.P., A.R. Putnam and J.H. Wright,
“A solid-state Maxwell demon”;
Foundations of Physics, October 2002, Vol. 32, No. 10.

D. Munteanu, G. Le Carval, G. Guegan,
“Non-Stationary Transport Effects: Impact on Performances of Realistic 50nm MOSFET Technology”
LETI, CEA / Grenoble, Microelectronics Department 17 rue des Martyrs, 38054 Grenoble, France

H. Väinölä, J. Storgards, M. Yli-Koski, and J. Sinkkonen,
“Light induced change on the built-in potential of p/p⁺ structures and its effect on carrier lifetime measurements”
Material Science and Engineering, B91-92, 2002, pp. 421-424.

X. F. Gao, J. J. Liou, A. Ortiz-Conde, J. Bernier and G. Croft,
“A physics-based model for the substrate resistance of MOSFETs”
Solid-State Electronics, Vol. 46, Issue 6, June 2002, pp. 853-857.

P. Masson, J. -L. Autran and D. Munteanu,
“DYNAMOS: a numerical MOSFET model including quantum-mechanical and near-interface trap transient effects”
Solid-State Electronics, Vol. 46, Issue 7, July 2002, pp. 1051-1059.

Wai-Kay Yip, Min Shen, Ming-C. Cheng, Robert Fithen and Goodarz Ahmadi,
“Hydrodynamic modeling of short-channel devices using an upwind flux vector splitting scheme”
Computer Methods in Applied Mechanics and Engineering, Vol. 191, Issue 47-48, Nov. 2002, pp. 5427-5445.

M. Masahara, T. Matsukawa, K. -I. Ishii, Y. Liu, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, E. Suzuki,
“15-nm-thick Si channel wall vertical double-gate MOSFET”
Technical Digest&International Electron Devices Meeting, 2002, pp. 949-951.

G. M. Laws, T. J. Thornton, J. Yang, L. De La Garza, M. Kozicki, D. Gust,
“Molecular control of the drain current in a buried channel MOSFET”
Physica Status Solidi (B) Basic Research, Vol. 233, Issue 1, September 2002, pp. 83-89.

F. Pregaldiny, C. Lallement, D. Mathiot,
“A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs”
Solid-State Electronics, Vol. 46, December 2002, pp. 2191-2198.

S. Persson, P. -E. Hellberg and S. -L. Zhang,
“A charge sheet model for MOSFETs with an abrupt retrograde channel: Part II. Charges and intrinsic capacitances”
Solid-State Electronics, Vol. 46, Issue 12, Dec. 2002, pp. 2217-2225.

M. Saxena, S. Haldar and M. Gupta, et al.,
“Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency”
IEEE Trans. Electron Devices, Vol. 49, Nov. 2002, pp. 1928-1938.

Fernando Gonz?z, Sr. , Suraj J. Mathew and J. Alex Chediak,
“A dynamic source-drain extension MOSFET using a separately biased conductive spacer”
Solid-State Electronics, Vol. 46, Issue 10, Oct. 2002, pp. 1525-1530.

X. Gao, J. J. Liou, J. Bernier and G. Croft,
“An improved model for substrate current of submicron MOSFETs”
Solid-State Electronics, Vol. 46, Issue 9, Sep. 2002, pp. 1395-1398.

L. Vestling, J. Olsson and K. -H. Eklund,
“Drift region optimization of lateral RESURF devices”
Solid-State Electronics, Vol. 46, Issue 8, Aug. 2002, pp. 1177-1184.

D. Munteanu, G. Le Carval and G. Guegan,
“Impact of technological parameters on non-stationary transport in realistic 50 nm MOSFET technology”
Solid-State Electronics, Vol. 46, Issue 7, Jul. 2002, pp. 1045-1050.

Seong-Dong Kim, et al.,
“Advanced model and analysis of series resistance for CMOS scaling into nanometer regime&part 1: theoretical derivation”
IEEE Trans. Electron Devices, vol.49, No.3, March 2002, pp.457&466.

C. Caillat, S. Deleonibus, G. Guegan, M. Heitzmann, M. E. Nier, S. Tedesco, B. Dal’zotto, F. Martin, P. Mur, A. M. Papon et al.,
“A 20 nm physical gate length NMOSFET with a 1.2 nm gate oxide fabricated by mixed dry and wet hard mask etching”
Solid-State Electronics, Vol. 46, Issue 3, March 2002, pp. 349-352.

Juin J. Liou, R. Shireen, A. Ortiz-Conde, F. J. Garcia Sanchez, A. Cerdeira, X. Gao, Xuecheng Zou and C. S. Ho,
“Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs”
Microelectronics Reliability, Vol. 42, Issue 3, March 2002, pp. 343-347.

Yee-Chia Yeo, Subramanian V. Kedzierski J., Peiqi Xuan, Tsu-Jae King, Bokor J., Chenming Hu,
“Design and Fabrication of 50-nm Thin-Body p-MOSFETs With a SiGe Heterostructure Channel”
IEEE Trans. Electron Devices, Vol. 49, Feb. 2002, pp. 279&286.

L. Mao, H. Nian, P. Gao, S. Zhang, W. Guo, S. Zhang,
“Mixed-mode circuit and device simulation for an optoelectronic integrated receiver”
Proceedings of SPIE&The International Society for Optical Engineering, Vol. 4919, 2002, pp. 507.

S. Persson, P. -E. Hellberg and S. -L. Zhang,
“A charge sheet model for MOSFETs with an abrupt retrograde channel: Part I. Drain current and body charge”
Solid-State Electronics, Vol. 46, Issue 12, Dec. 2002, pp. 2209-2216.

B. Villard, F. Calmon, C. Gontrand,
“Design and characterization of high voltage devices integrated in a standard CMOS technology”
EPJ Applied Physics, Vol. 16, Issue 2, November 2001, pp. 113-120.

Milne PR,
“Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter”
Naval Postgraduate School, Monterey, CA. Sep 2001. 97p. NTIS ADA397177.

G. Kamoulakos, Y. Tsiatouhas, A. Chrisanthopoulos and et al.,
“A high-density DRAM cell with built-in gain stage”
IEEE Trans. Electron Devices, Vol. 48, Jun. 2001, pp. 1194&1199.

D. Munteanu, G. Le Carval, G. Guegan,
“Impact of non-stationary transport effects on realistic 50nm MOS technology”
2001 International Conference on Modeling and Simulation of Microsystems&MSM 2001, 2001, pp. 46.

N. Takaura, R. Nagai, H. Asakura, S. Yamada, S. Kimura,
“A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design”
IEEE International Conference on Microelectronic Test Structures, 2001, pp. 171-176.

J. Kang, X. He, D. Vasileska and D. K. Schroder,
“Optimization of FIBMOS through 2D Silvaco ATLAS and 2D Monte Carlo particle-based device simulations”
VLSI Design, Vol. 13, No. 1-4, 2001, pp. 251-256.

F. Duvivier, E. Guichard,
“Worst-case SPICE model generation for a process in development using ATHENA, ATLAS, UTMOST and SPAYN”
The 13th IEEE International Conference on Microelectronics (ICM 2001), pp. 11 -18.

W. Zagozdzon-Wosik, L. Shao, M. Menon, E. Arroyo-Castelazo, I. Rusakova, X. Wang, P. van der Heide, J. Liu, W. K. Chu and J. Bennet,
“Device and material issues related to integration of junctions with contacts in deep 0.1 /spl mu/m MOSFETs”
Advanced Thermal Processing of Semiconductors 9th IEEE International Conference on RTP 2001, pp. 82.

Allibert F. Zaslavsky A. Pretet J. Cristoloveanu S.,
“Double-Gate MOSFETS : Is Gate alignment Mandatory?”
Proc. ESSDERC 2001.

Schwantes S. Krautschneider W.,
“Relevance of Gate Current for the Functionnality of Deep Submicron CMOS Circuits”
Proc. ESSDERC 2001.

Landgraf E. Rösner W. Luyken R.J.,
“High On Current in Quasi Double Gate Transistors with Undoped Channel Region”
Proc. ESSDERC 2001.

D. Y. Chung and J. H. Lee,
“Design consideration of self-aligned recessed channel (RC) devices in sub-100 nm CMOS technology”
Journal Korean Phys. Soc., Vol. 37, Nov. 2000, pp. 617&623.

C. W. Liu and T. X. Hsieh,
“Analytic modeling of the subthreshold behavior in MOSFET”
Solid-State Electronics, Vol. 44, Issue 9, 1 September 2000, pp. 1707-1710.

C. Fink, K. G. Anil, H. Geiger, W. Hansch, J. Schulze, T. Sulima and I. Eisele,
“Optimization of breakdown behaviour and short channel effects in MBE-grown vertical MOS-devices with local channel doping”
Thin Solid Films, Vol. 369, Issues 1-2, 3 July 2000, pp. 383-386

J. Kang, J, X. He, D Vasileska, D.K. Schroder,
“Optimization of FIBMOS through 2-D device simulations”
Book of Abstracts. IWCE Glasgow 2000. 22-25 May 2000 pp. 87 -88.

S. Williams and K. Varahramyan,
“New TCAD-based statistical methodology for the optimization and sensitivity analysis of semiconductor technologies”
IEEE Trans. Semiconductor Manufacturing, Vol. 13, May 2000, pp. 208-218.

Yun-Gueon Shin and Jong-Hwa Lee,
“A study of electrical characteristics and reliability on flash EEPROM cell”
Proceedings of the 4th IEEE Korea-Russia International Symposium on Science and Tech, Vol. 2, 2000.

V. Narayanan et al,
“Reduction of Metal-Semiconductor Contact Resistance by Embedded Nanocrystals”
Proc. IEDM 2000.

K. G. Anil et al,
“Role of Inversion Layer Quantization on Sub-Bandgap Impact Ionization in Deep-Sub-Micron n-channel MOSFETs”
Proc. IEDM 2000.

Monfray S. Autran J.L. Jurczak M. Skotnicki T.,
“Self-Consistent Optimization and Performance Analysis of Double-Gate MOS Transistor”
Proc. ESSDERC 2000, pp. 336-339.

Tsamis C. Tsoukalas D. Tserepi A.and Tsoi E.,
“The Influenceof Silicon Intersticial Clusters on the Reverse Short Channel Effect”
Proc. ESSDERC 2000, pp. 172-175.

F. Roger et al,
“New Calibration Method Of Analytical Models For Ion Implantation”
IWSM 2000, Honolulu, pp. 18-21.

A. Armigliato, R. Balboni, S. Balboni, S. Frabboni, A. Tixier, G. P., Carnevale, P. Colpani, G. Pavia, A. Marmiroli,
“TEM/CBED determination of strain in silicon-based submicrometric electronic devices”
Micron, Vol. 31, Issue 3, June 2000, pp. 203-209.

He, Xiaojiang,
“Two-dimensional Monte Carlo particle-based simulations of ultra-small MOSFETs”
MS, Arizona State Univ, 2000, 75 pp. AAT 1398445.

Williams S. and Varahramyan K.,
“New TCAD-based statistical methodology for the optimization and sensitivity analysis of semiconductor technologies”
IEEE Transactions on Semiconductor Manufacturing, Vol. 13, Issue 2, May, 2000, pp. 208-218.

A. Inani, R. V. Rao, B. Cheng, J. Woo,
“Gate Stack architecture analysis and channel engineering in deep sub-micron MOSFETs”
Japanese Journal of Applied Physics, Part 2: Letters, Vol. 38, Issue 4 B, 1999, pp. 2266-2271.

M. Kataoka, K. Komuro, K. Fujita and A. Taniguchi,
“Analysis of 0.5 m channel Al/WSix/Poly-Si gate performance in high-frequency band Si power MOSFETs with process/device/circuit continuous simulation”
Solid-State Electronics, Vol. 43, Issue 9, September 1999, pp. 1689-1694.

G. Schrag, G. Zelder, H. Kapels and G. Wachutka,
“Numerical and experimental analysis of distributed electromechanical parasitics in the calibration of a fully BiCMOS-integrated capacitive pressure sensor”
Sensors and Actuators A: Physical, Vol. 76, Issues 1-3, 30 August 1999, pp. 19-25.

D. Munteanu, S. Cristoloveanu, and E. Guichard,
“Numerical simulation of the pseudo-mosfet characterization technique”
Solid-State Electronics, 43(3):547-554, March 1999.

G. -F. Dalla Betta, P. Bellutti, M. Boscardin, L. Ferrario, G. Soncini and N. Zorzi,
“An all-implanted p-channel Si JFET fully compatible with CMOS technology”
Microelectronics Journal, Vol. 30, Issue 3, March 1999, pp. 281-285.

J. Moers, et al.,
“Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth”
Solid-State Electronics, Vol. 43, March 1999, pp. 529-535.

A. Inani et al,
“Capacitance degradation dur to fringing fields in deep sub-micron MOSFETs with high-k gate dielectrics”
ESSDERC 1999, pp. 160-163.

W. Vanderbauwhede et al,
“Efficient methodologies for statistical characterisation of analogue designs for submicron CMOS technologies”
ESSDERC 1999, pp. 468-471.

Kun. H. To and Jason Woo,
“60nm T-gate MOSFETs with self-aligned drain extension formed by solid phase diffusion”
Proc. DRC’99, pp. 24-25.

D. Y. Chung and J. H. Lee,
“Effects of recess channel (RC) depth in super self-aligned RC nMOSFET’s for sub-100 nm device technology”
Journal Korean Phys. Soc., Vol. 33, Nov. 1998, pp. 216&219.

B. Szelag and F. Balestra,
“Substrate bias dependence of the transconductance of deep submicron silicon NMOSFETs”
Solid-State Electronics, Vol. 42, October 1998, pp. 1827-1829.

B. Szelag, and F. Balestra,
“Transconductance enhancement at low temperatures in deep submicrometre MOSFETs”
Electron Letter, Vol. 34, Sep. 1998, pp. 1793-1794.

W. Hansch, V. Ramgopal Rao, C. Fink, F. Kaesen and I. Eisele,
“Electric field tailoring in MBE-grown vertical sub-100 nm MOSFETs”
Thin Solid Films, Vol. 321, Issues 1-2, 26 May 1998, pp. 206-214.

B. You and A. Q. Huang,
“Theoretical limitation of the RBSOA of MOS-controlled thyristors”
Solid-State Electronics, Vol. 42, Issue 5, May 1998, pp. 785-794.

G. A. Armstrong and Chinmay K. Maiti,
“Strained-Si channel heterojunction p-mosfets”
Solid-State Electronics, Vol. 42, Issue 4, April 1998, pp. 487-498.

T. Gaillard, H. Lhermite, O. Bonnaud and K. Kis-Sion,
“Calibration of polycrystalline silicon deposition and etching machine inside a technological simulator”
Computational Materials Science, Vol. 11, April 1998, pp. 109-112.

B. Cheng, V. Ramgopal Rao, et al,
“Realization of 0.1um asymmetric channel MOSFETs with excellent short-channel performance and reliability”
ESSDERC 1998, pp. 520-523.

I. Ban, M. C. Ozturk and E. K. Demirlioglu,
“Suppression of oxidation-enhanced boron diffusion in silicon by carbon implantation and characterization of MOSFET’s with carbon implanted channels”
IEEE Trans. Electron Devices, Vol. 44, Sep. 1997, pp. 1544&1551.

P. A. Clifton, S. J. Lavelle and A. G. O’Neill,
“Sub-micron strained Si:SiGe heterostructure MOSFETs”
Microelectronics Journal, Vol. 28, Issues 6-7, 9 August 1997, pp. 691-701.

T. Endoh, T. Nakamura and F. Masuoka,
“An accurate model of fully-depleted surrounding gate transistor (FD-SGT)”
IEICE Trans. Electron, E80C, Jul. 1997, pp. 905&910.

T. Endoh, T. Nakamura and F. Masuoka,
“An analytic steady-state current-voltage characteristics of short channel fully-depleted surrounding gate transistor (FD-SGT)”
IEICE Trans. Electron, E80C, Jul. 1997, pp. 911&917.

C. Leveugle, P. K. Hurley, A. Mathewson, S. Moran, E. Sheehan, A. Kalnitsky, A. Lepert, I. Beinglass and M. Venkatesan,
“Impact of the polysilicon doping level on the properties of the silicon/oxide interface in polysilicon/oxide/silicon capacitor structures”
Microelectronic Engineering, Vol. 36, June 1997, pp. 215-218.

B. Szelag and F. Balestra,
“On the transconductance enhancement at low temperature in deep submicron MOSFETs”
Proc. ESSDERC’97, pp. 384-387.

P. Sallagoity, M. Ada-Hanifi and A. Poncet,
“Cost effective simulation of three dimensional effects in the shallow trench isolation process”
Proc. ESSDERC 1997, pp. 468-471.

A. Sridharan et al,
“Mechanism of localized charge injection: A technique to characterize gate edge damage in MOS transistors”
Proc. ESSDERC 1997, pp. 560-563.

W. Hansch, V. Ramgopal Rao and I. Eisele,
“The planar-doped-barrier-FET: MOSFET overcomes conventional limitations”
Proc. ESSDERC 1997, pp. 624-627.

G. Lecarval et al,
“Methodology for predictive Calibration of TCAD Simulators”
Proc. SISPAD 1997, pp. 177-180.

V. Ramgopal, W. Hansch and I. Eisele,
“Simulation, Fabrication and Characterisation of High Performance Planar-Doped-Barrier Sub 100nm Channel MOSFETs”
Proc. IEDM, pp. 1997.

P. Fouillat, H. Lapuyade, Y. Maidon and J. P. Dom,
“Analysis of Latchup susceptibility to internal logical states by using a Laser beam”
Microelectronic Engineering, Vol. 31, Issues 1-4, February 1996, pp. 79-86.

P. Sallagoity, M. AdaHanifi, M. Paoli and et al.,
“Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies”
IEEE Trans. Electron Devices, Vol. 43, Nov. 1996, pp. 1900-1906.

V. R. Rao, F. Wittmann, H. Gossner and et al.,
“Hysteresis behavior in 85-nm channel length vertical n-MOSFET’s grown by MBE”
IEEE Trans. Electron Devices, Vol. 43, Jun. 1996, pp. 973&976.

E. Vandenbossche,
“Analysis of S/D engineering through short channel effect and hot carrier injection behavior in a 0.35um CMOS technology”
ESSDERC 1996, pp. 491-494.

P. A. Clifton,
“A process for strained silicon n-channel HMOSFETs”
ESSDERC 1996, pp. 519-522.

L. Risch et al.,
“Channel engineering using RP-CVD epitaxy for high performance CMOS transistors”
ESSDERC 1996, pp. 321-324.

A. Kl,
“A new analytical method of solving 2D Poisson’s equation in MOS devices applied to threshold voltage and subthreshold modeling”
Solid-State Electronics, Vol. 39, December 1996, pp. 1761-1775.

I. Eisele, H. Baumgatner and W. Hansch,
“Silicon nanostructure devices”
Journal of Crystal Growth, Vol. 157, Issues 1-4, December 1995, pp. 248-254.

L. Perron et al,
“Electron Mobility in highly doped MOSFET’s with standard and nitrided gate oxide”
Proc ESSDERC 95, The Hague, Netherlands, pp. 113-116.

Dr. Bruno Baccus, ISEN and Peter Hopper, Silvaco
” “ISEN Advanced Diffusion and Oxidation Models Slated for Inclusion in ATHENA “”

Michael Duane, Advanced Micro Devices (AMD), FAB 25
” “A User’s Perspective on Simulator Calibration “”

Jarvis B. Jacobs, Dimitri Antoniadis,
“Channel Profile Engineers for MOSFET´s with 100 nm Channel Lenghts”
IEEE Trans on Electron Devices Vol. 42, No. 5, May 1995.

D. Uffmann et al.,
“Latchup design precautions for 1.0 micron junction isolated CMOS ASICs operating at temperatures up to 525K”
Proc. ESSDERC 1994, pp. 675-678.

G. Le Carval et al.,
“Advantages of the methodology using DOE and simulation for optimising advanced technologies&application to a real 0.35um PMOS architecture”
Proc. ESSDERC 1994, pp. 841-844.

T. Skotnicki et al.,
“A new analog/digital CAD model for sub-half micron MOSFETs”
Proc. IEDM Tech. Dig., 1994, pp. 165-168.