We analyze quantitatively the real impact of technology on the needed level for carrier transport modeling. The results, based on theoretical analyzes, are applied to existing devices. This work shows which recipes must be used to evaluate the performances of advanced device architectures (down to 50nm gate length). An original point of this work is the investigation of technology influence (channel doping and LDD doping) on injection velocity at source side and on drain current. The results open the perspective of specific engineering of access regions in order to take full advantage of non-stationary effects on the drain current.

This article presents a high frequency SPICE model parameter extraction method for CMOS devices. Current compact MOS models are developed for low frequency applications and provide good fits for DC, conductances and intrinsic capacitances. However for the gigahertz frequency range external components have to be modeled and added to the compact model as macro model elements. The macro model presented in this article provides good results up to 10 GHz.

This routine is a multitarget/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets. This routine is based on full SMU definition. This definition could be done for 3 different targets grouped together in 4 different setup. It means that 12 different bias conditions can be defined. One device is associated with one setup therefore with one, two or three targets.Application

This routine is a multitarget/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets. This routine is based on full SMU definition. This definition could be done for 3 different targets grouped together in 4 different setup. It means that 12 different bias conditions can be defined. One device is associated with one setup therefore with one, two or three targets.

Cross-Sectional Viewer is a tool within Expert to simulate the cross sectional view of ICs along an arbitrary drawn cut-line on the layout. Cross-sectional Viewer is a link between the layout and the resulting device. It allows the designer to examine cross-sections of the device being designed. Cross-sectional drawings are useful for understanding design rules, parasitic coupling and other design and fabrication problems.

An important step in electronic circuit design is layout versus schematic verification (LVS)