엔트리 Gigi Boss

FinFET 및 메모리 애플리케이션에서 Victory Process TCAD 기하학적 식각 모델 활용

2023년 5월 19일 2:00am-2:30am (한국 시각)
이번 시간에 FinFET 및 메모리 애플리케이션이라는 면에서 기하학적 식각 모델을 제시합니다. 핀 형상 구성, 이상적이지 않은 식각 프로파일 (bowing, twisting) 및 자체 정렬 공정 (다중 패턴화)을 실현하기 위한 기술을 소개합니다.

Simulation Framework for Device-packaging Co-design for Power Electronics

The past several years has seen a fast deployment of wide-bandgap power devices in fast chargers, electric vehicles, data centers and renewable energy processing. The performance of power devices is fast progressing towards their intrinsic material limit. As these devices can handle higher voltage and larger current density, packaging and thermal management will become the key limiting factor for exploiting their benefits in power electronic converters and systems.

Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations

The utilization of thin material layers is common in modern semiconductor device fabrication. Subsequent etching steps require an accurate modeling of these thin layers. Although level-set based process TCAD simulations are capable of representing flat thin material layers with sub-grid accuracy, topographical changes during etching processes expose the low underlying grid resolution, which leads to detrimental artifacts.