Introduction

As MOS field-effect transistors are scaled down to a nanometer regime, quantum effects in both transverse and transport directions start playing a major role in determining device characteristics. In order to address a new challenge, SILVACO has started a deployment of new quantum mechanical models based on Non Equilibrium Green’s Function (NEGF) approach. This is a fully quantum mechanical approach which treats such effects as source-to-drain tunneling, ballistic transport, and quantum confinement on equal footing. The new NEGF solver is suitable to model ballistic quantum transport in such devices as Double Gate or Surround Gate MOSFET, using rectangular or cylindrical geometries in ATLAS. The method used is based on references [1] and [2].

Introduction

In recent years, the investigation of Organic Light Emitting Diodes (OLEDs) and photovoltaic devices based on small organic molecules and polymers has attracted significant interest due to their potential for inexpensively generated electricity. ATLAS has been used already to investigate OLEDs [1] and compound material GaInP[2][3] devices.

Abstract

This paper is focused on the stability of n-channel laser-crystallized polysilicon thin-film transistors (TFTs) submitted to a hydrogenation process during the fabrication and with small grains dimension. With the aid of numerical simulations, we investigate the effects of static stress using two types of procedures: the on stress and the hot carrier stress. Results show that the variations of trap state density into the whole polysilicon layer and not only near the drain junction are responsible for the degradation of TFTs performances in both the two types of stress and that the interface trap states play a negligible role compared to the bulk trap states.

Introduction
The trend toward ultra-short gate length MOSFET requires a more and more effective control of the channel by the gate leading to new architecture like double-gate, tri-gate, omega-gate, and four-gate (or gate-all-around) MOSFETs. Recent advances in nanoscale fabrication techniques have shown that semiconductor nanowires are becoming promising candidates for next generation technologies. In particular, silicon nanowire transistors have been demonstrated by several research groups with cross-sectional dimensions in the range of several nanometers.

Introduction

It is widely believed that the scaling of standard Flash devices will face in a near future several limitations, due to the high voltage requirement of the program/erase and the stringent charge storage requirement of the dielectrics [1]. Among the possible solutions to push further the scaling limits of standard technologies, Si nanocrystal (Si-NC) memories are one of the most promising. It has been shown that thanks to the discrete nature of Si-NC, thinner tunnel oxide can be used (allowing lower operating voltages), without compromising the reliability [2, 3]. Indeed, a first understanding of the Si-NC memory behaviour can be achieved through simplified/semianalytical models [4, 5, 6]. Nevertheless, these approaches are not enough accurate to allow the optimization of the technological parameters, especially for NOR cells, written by channel hot electron (CHE) injection. To this aim, more complex numerical models, which take into account twodimensional (2D) or even three-dimensional (3D) effects, should be used.