At our SURGE Santa Clara event in October, Cameron Fisher, CEO of Mobile Semiconductor described their experience in adopting SmartSpice as their characterization engine for creating the database for their Trailblaze™ memory compiler software. Below is a summary of his talk.
The IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. It is the flagship conference for
Nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices
Novel quantum and nano-scale devices and phenomenology
Optoelectronics, devices for power and energy harvesting, high-speed devices
Process technology and device modeling and simulation
2018년 12월 7일 | 시각: 3:00am-3:30am (한국 시각)
인공지능(AI)과 머신러닝(ML) 기반 SoC의 개발 과제를 논의합니다.
Abstract— A complete simulation flow for a Nanowire-based ring oscillator circuit is presented, where the active devices were simulated using an atomistic device simulator. The results of this simulation have been fitted to an active device SPICE compact model, specifically formulated for nanowire/Gate all around Field Effect Transistors” (FETs). Finally, the active devices were incorporated into a SPICE netlist including back end resistance and capacitance parasitics.
Abstract—There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problems and it needs to provide enough current during read and erase operation. In this paper, we examined the design optimization of select gate transistor with respect to various device elements including work-function, S/D overlap, and trap density. Finally, we reviewed the path to reduce the channel length of the select gate transistor in conjunction with the role of dummy cells.
In this paper, in order to understand trap-rich substrate behavior, passive and active device on SOI with trap-rich layer structures were simulated using the Victory Device simulator. Harmonics distortion of devices were also compared.
Introduction
Diamond is considered to be the ultimate semiconductor material for high power and high frequency devices due to its superior electrical and thermal properties, such as high breakdown field, high carrier mobility, low dielectric constant, and high thermal conductivity, as shown in Table 1.
Furthermore, diamond has some unique electronic properties. The surface of diamond films terminated by hydrogen atoms has negative electron affinity (NEA) and can generate a two-dimensional hole accumulation layer suitable as a hole channel of a field-effect transistor.
Introduction
Gallium nitride (GaN)-based devices are excellent candidates for high-voltage and high-power applications, due to the superior physical properties of GaN compared to Si, SiC, and GaAs. Recently, GaN vertical devices have attracted increased attention, due to their advantages over GaN lateral devices, including high breakdown voltage (BV) and current capability for a given chip size, and superior thermal performance.1 Recent demonstrations of high-performance vertical GaN diodes2–4 and transistors5–9 have made vertical structures very promising for GaN power devices.
Introduction
Amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) show a high mobility, a small sub-threshold swing, and a low OFF-current, and they are considered to be one of the most promising TFT for new flat-panel displays (FPDs). The high mobility originates from the unique electron transport in a-IGZO. The transport properties are different from those in conventional semiconductor materials like Si, for example, the mobility increases with increase of the electron concentration and/or temperature. Therefore, the new mobility model for a-IGZO is necessary. In addition, as pixel sizes in the FPDs decreases, a channel-length, L, of a-IGZO TFTs becomes shorter. It indicates that it is important to understand the operation of short-channel a-IGZO TFTs.
Abstract — Dual junction solar cells were simulated using Silvaco TCAD tool with various tunnel junction material compositions. InGaP/GaAs dual junction solar cells were simulated with 10 different tunnel junction combinations. The highest efficiencies were from InGaP/AlGaAs and InGaP/InGaP tunnel junctions at 31.82% and 31.75%. InGaP/CdTe solar cells were also simulated with four different tunnel junction combinations. InGaP/InGaP tunnel junction was found to be most efficient with 37.29% which is consistent with experimental data. Three of four InGaP/CdTe dual junction solar cells were simulated to have higher efficiency values than all InGaP/GaAs solar cells.