Compound Devices

CMOS Technology

Process Simulation

Weebit Nanoとシルバコ、ReRAMの採用を促進するシミュレーションの新機能を開発

2020年2月19日 - 全世界の半導体業界に向け次世代メモリ・テクノロジの開発を行うWeebit Nano Ltd (ASX: WBT) と、電子システム設計用ソフトウェア、IP、サービスの世界的リーディング・プロバイダであるSilvaco Inc. (以下シルバコ) は、本日、Weebitのシリコン酸化物 (SiOx) 抵抗変化型メモリ (ReRAM) デバイスについて電気的振る舞いのモデリングに成功したことを発表しました。

Victory Atomisticによる革新的ナノデバイスのTCADシミュレーション

本ウェビナーでは、シルバコのTCADツール・スイート群の一つであるVictory Atomistic (VA) のシミュレーション機能を紹介します。

Two-dimensional oscillatory neural networks for energy efficient neuromorphic computing

Feb. 5, 2020 On the 4 th and 5th of February 2020, in Montpellier (France), at the premises of LIRMM, CNRS the Kick-off meeting of NeurONN took place. All the Partners of the NeurONN Consortium met and set the ground for the activities along the three-year duration of the EU Project

For Next Generation Nanowires, Simulation from Atoms to SPICE

As process nodes continue to shrink, the requirement for additional physics-based simulation is gradually creeping into each stage of the design process. By way of illustration, Technology Computer Aided Design (TCAD) simulations are becoming more atomistic in nature, SPICE models are becoming process aware to take account of localized strain effects, and back or middle end of line (BEOL or MEOL) parasitics are moving from exclusively two-dimensional (2D) rule-based solutions to full 3D structure field solvers for numerous critical sections of the layout.

Atomistic Analysis and Next Generation Computing at IEDM 2019

IEDM is THE device conference with more than a thousand participants from major companies and R&D institutes. Many talks were dedicated to new memory devices and circuits, including Ferroelectrics, MRAM, RRAM, driven by the requirements of AI processing. EUV is definitely there for 3nm and beyond. 3D integration was shown for LP-HP logic and RF. Gate-All-Around devices, with nanowires or nanosheets are mature versus FinFET.

TCAD Recommended Textbooks

CMOS: Mixed-Signal Circuit Design, Second Edition R. Jacob Baker. Published…

3次元NANDメモリ・セルのセレクト・ゲート・トランジスタ最適化

本ウェビナーでは、セレクト・ゲート・トランジスタに注目した3次元NANDメモリ・セル動作の最適化で、TCADプロセスおよびデバイス・ソフトウェアをどのように利用できるかを紹介します。