Using SmartSpice Compact Models
This webinar will provide a guide to developing Compact Models in SmartSpice to achieve optimal simulation performance. You will learn how models are used in SmartSpice and best practices when constructing a custom Verilog-A model. You will also learn about built-in simulator models versus custom Verilog-A models and how to look at the circuit simulation results to debug your model. This will lead to a better understanding of SmartSpice to get good simulations and allow you to explore circuit behavior. Examples and templates, available online, will also be introduced to help meet general simulation requirements.
Presenter
Colin is a Chartered Engineer with over 30 years of experience in the semiconductor industry. He has worked on production/development of device process for both silicon and III-V compounds as well as device/circuit design covering test structure, SRAM, IGBT, and SAW filters. He has characterized a wide range of devices including low power, RF, radiation hardened, and power devices used in passenger trains. He is currently Silvaco’s Compact Modeling Coalition (CMC) and Si2 representative and he is active in the simulation of the latest circuit devices. Colin has a BSc in Physics from the University of Surrey.
When: June 11, 2020
Where: Online
Time: 10:00am-10:30am-(PDT)
Language: English
WHO SHOULD ATTEND:
Academics, engineers and management looking for solutions to circuit design and physical verification in ultra-thin chip, thin-film and hybrid flexible electronics.