High speed Interface Design: Best Practices
This webinar will provide a presentation on challenges and solutions associated with the development of high-speed interface design in modern SOCs. Recent breakthroughs in semiconductor process technology allow for extreme high-speed interface designs which open the door to efficient chips with increased density, fast and reduced power consumption at applications like smart cities, AI/ML, and autonomous driving. During the last 15 years there has been significant development in realizing high speed and bandwidth memories, and extreme high-speed Interfaces. Silvaco’s production proven design IPs for high speed memory and interconnects match these developments.
What attendees will learn:
- Key challenges of designing high-speed interfaces.
- Best practices in high-speed interface design for SOCs
- Powerful offerings of IPs by Silvaco
Presenter
Ahmad S. Mazumder is a Principal Field Application Engineer in the IP Business Unit of Silvaco. He is responsible for development and customer support in all analog and Interface IPs. He is an Industry veteran on the development of high-speed memory & interface IPs and diverse types of analog IPs. He worked on cutting edge DDR, extreme High-speed Serdes, interfaces, ESD, quality and reliability for 24 years at various SOC companies – Intel, Broadcom, C-Cube Microsystems.
Mazumder holds an MS in VLSI Semiconductor Design from the City University of New York, and a BS in Electrical & Electronics Engineering from Bangladesh University of Engineering and Technology.
WHO SHOULD ATTEND:
Engineers, architects, and management looking for solutions to design and optimize high-performance SoCs
When: August 27, 2020
Where: Online
Time: 10:00am-10:30am – (PDT)
Language: English