Achieve Your Display Design Performance Edge Through Precision Parasitic Extraction

Increasingly restrictive design rules and nonplanar surface topography severely limits a designer’s options for innovation using traditional rules-based extraction tools. Silvaco Hipex-FS can help designers find that edge in performance and innovation with the full force of realistic 3D process simulation.

Traditional Resistance and Capacitance extraction (RCx) tools have a general limitation because the final structure is simplified before calculation of interconnect parasitics. This limitation results in significant errors of interconnect parasitic resistance and capacitance extraction, forcing the circuit designer to increase margins for error in their designs resulting in less than optimum circuit performance.
Silvaco is addressing these issues by providing the circuit designer with a highly accurate realistic 3D process simulation to create a structurally correct back-end process for critical areas. Multiple options are provided for creating realistic back-end 3D structures within the same design, which coupled with proprietary domain decomposition techniques allow larger area circuits to be simulated accurately all from a single user interface.

What You Will Learn

• Develop a greater understanding of new developments in Silvaco RCx solution
• Simulate 3D BEOL using Silvaco Victory Process solution
• Use of a single user interface combining rule and Field solver-based RC extraction
• How to reduce margins through precision RCx

Presenter

Derek Kimpton has been with Silvaco in front end technology (TCAD) and back end of line (BEOL) Field Solver Applications Department for nearly quarter century, supporting numerous different types of technology.
Prior to his time at Silvaco, he was working with highly radiation tolerant silicon-based designs in the characterization department, for space and defense applications, and in the synthesis of SiGe layers on silicon by germanium implantation. His first degree in electronics and PhD on designing GaInAs based devices was obtained at King’s College London.

WHO SHOULD ATTEND:

Circuit designers, display designers, academics and engineering and product management.