Simulating the Hysteresis effects of Si/SiO2 Interface Traps

Introduction

The trap states at the interface of Silicon with Silicon Dioxide are usually divided conceptually into interface states and fixed oxide charges [1]. These trap states can cause the degradation of the performance of devices such as MOSFETs, when they are stressed into a regime where hot carriers are significant. This degradation is usually permanent and occurs for stress times of the order of 10³ seconds [2]. This phenomenon is well studied, and ATLAS has a degradation model for simulating these effects [3].

If a MOSFET is stressed so as to avoid significant hot carrier current, the threshold voltage V_t can show hysteresis effects on the sub-second time scale [4]. This can affect the settling time of circuits containing MOSFETs. It is proposed in [4] that the mechanism for the hysteresis is tunnelling of electrons directly from the channel into the fixed oxide traps, as well as indirectly, via the interface states. The experimentally observed dependence of hysteresis on measurement time is apparently predicted by the model of Heiman et al [5]. This model is implemented in ATLAS and can be used to simulate hysteresis effects due to oxide trapping. [6] In the next section we describe this model and its implementation in ATLAS. Some examples of its use are then described.