Victory Process 2D – A Valuable Alternative To SUPREM-based Simulators
1. Introduction
SUPREM-IV – Stanford University PRocEss Modeling Program was first released 30 years ago. Since then its descendants – Athena from Silvaco and TSUPREM-4TM from TMA/Avant/Synopsys – have been 2D process simulation “work-horses” in semiconductor industry world-wide. Despite the fact that tremendous progress in the industry indeed requires the transition to 3D TCAD there are still many technologies and applications where a 2D simulation is the most practical approach. At the same time, we have to recognize that the SUPREM-based simulators cannot keep up with the progress because they lack many fundamental capabilities required for simulation of modern processes. Victory Process (VP) has been developed by Silvaco to address these challenging requirements. Though ultimate purpose of VP is accurate simulation of complex 3D process it still can be used as a valuable alternative to or even advantageous substitution for SUPREM based simulators. The 2D-mode of Victory Process (VP2D) differs from the full 3D mode only by setting a 2D simulation domain when simulation starts. This means that the same syntax, models, algorithms, layout and the whole process flow can be used in both 2D and 3D. This guarantees smooth transition from 2D to 3D process simulation.
In this paper, we will outline similarities and differences between Athena and VP2D. Also, we show advantages of VP2D as better designed, more generic and reliable process simulator. We only briefly discuss individual models and capabilities of VP but mainly focus on practical advantages of VP2D – efficiency of algorithms and methods, mesh control and reliability within Virtual Wafer Fab (VWF). Finally, we will demonstrate some key capabilities and advantages of VP2D by using example of process simulation of a UMOS device.
