Optimization of PD-SOI CMOS Process and Devices for RF Applications

In recent years, radio-frequency (RF) CMOS on Silicon-on-Insulator (SOI) has rapidly evolved as a mainstream technology for switches used in wireless applications such as tuners and power amplifiers [1, 2]. Since such applications can involve switching high power levels at high frequencies (~2 GHz), the technology considerations are substantially different than those for SOI used in high speed, small signal applications such as microprocessors. Requirements of lower insertion loss, better isolation, and better linearity have driven RF CMOS-SOI roadmap.

‘On-resistance’ (Ron) of a FET plays a key role in insertion loss of switches. Ron is a combination of channel resistance and resistance of source-drain extensions as well as that of interconnects. Among these, channel resistance is the largest contributor. Consequently, aggressive reduction in channel length is a routinely adopted method to reduce Ron [1].

‘Off-capacitance’ (Coff) is normally associated with isolation between ports of a switch; lower capacitance resulting in better isolation. Coff is a combination of a number of linear (interconnects) and nonlinear (gate, gate-to-source/drain, junctions, buried oxide) capacitances. Silicon thickness plays a key role in controlling Coff. A typical RF CMOS-SOI offering today is partially depleted, with ~0.15µm thick Silicon layer. Partially depleted (PD)-SOI reduces/eliminates multiple components of junction capacitances [4], resulting in lower Coff than triple-well bulk CMOS and SOI with thicker (~1µm) Silicon.