Mixed-Signal Simulation with SmartSpice in the Cadence Design Framework II

Users of the Cadence Design Framework II (DFII, versions 4.4.0 and above) have been enjoying a tight integration between SmartSpice and the Analog Artist Electrical Design System and Composer Design Entry tools. This integration is achieved via the Cadence Spice Socket (cdsSpice) and the Open Analog Simulation Integration Socket (OASIS). It has been comprehensively documented in previous issues of the Simulation Standard, and also in a new application note (Ref No. SS/99-2).

The SmartSpice Interface to DFII already supports automatic netlisting, cross-probing, back-annotation and many other standard features of the DFII simulation environment. In a significant upgrade, the latest release also allows the user to make SmartSpice the analog component of their DFII mixed-signal design and simulation environment, with Cadence Verilog-XL supplying the digital simulation capability. The additional integration code is distributed in the form of a mixed-mode context file. A context file is compiled SKILL code, which is installed into the Cadence installation hierarchy along with the pre-existing analog context file, and many other related files, with the command: