Secrets of Parasitic Extraction Unveiled!
Parasitic extraction is a mandatory step for physical design sign off, and at advanced nodes, parasitics substantially impact the behavior of circuit design. Any analysis must consider the interconnect parasitic effects to produce meaningful and realistic results. In this webinar, we will review a flow that can qualitatively and quantitatively compare two extraction flavors for the same design. We will then present an in-depth exploration of exactly where the differences are coming from. At the end of this webinar, switching between different layout parasitic extraction tools, calibrating settings to a new technology node, qualifying PDK updates etc will no longer be a bottleneck for CAD teams.
What attendees will learn:
- Powerful and accurate methods to qualify and quantify different parasitic extraction methods
- How to recognize traps in the flow and possible work-arounds
- How to explore parasitics and analyze what is different and where
Presenter
Mr. Jean-Pierre Goujon is Application Manager for Silvaco France. He is responsible for customer technical support for EDA products, with a specific interest in parasitic analysis and reduction products. Prior to this position, he has been AE manager for Edxact for 12 years and had various AE responsibilities at Cadence, Simplex and Snaketech mostly in the field of parasitic extraction.
Mr. Goujon holds a BSc in EEE from Robert Gordon University, Aberdeen, UK and a MS in EEE from Ecole Supérieure de Chimie, Physique, Electronique de Lyon, France.
When: March 23, 2017
Where: Online
Time: 10:00am-11:00am-(PST)
Language: English
WHO SHOULD ATTEND:
Designers who care about the quality of physical designs. CAD Engineers and PDK Engineers who work on parasitic extraction rules and ensure the quality of the parasitic extraction.