| Time | Topic | Speaker |
| 9:00 AM | Introduction and Agenda | |
| 9:10 AM | Why Am I Here? | Wally Rhines, Silvaco, Inc. |
| 9:30 AM | Keynote - Memory Innovations: Empowering the AI Revolution to drive Chip Technology Development | Gurtej Sandhu, Micron Technology, Inc. |
| Time | Topic | Speaker |
| 10:00 AM | Ramping Manufacturing to Production Using Physics-based Digital Twins | Garrett Schlenvogt, Silvaco, Inc. |
| 11:00 AM | Unified 3DEXPERIENCE Platform for Accelerating Semiconductor Manufacturing Innovation | Emmanuel Leroux and Morteza Mosheni, Dassault Systèmes |
| 11:30 AM | Advanced Logic FinFET/Nanosheet Simulation with Silvaco Victory Tools | Zhenhua Wu，Zhejiang University |
| Accelerating Next Generation Power Technologies Track | ||
|---|---|---|
| Time | Topic | Speaker |
| 10:00 AM | Accelerating Next Generation Power Technologies | Britt Brooks, Silvaco, Inc. |
| 10:30 AM | TCAD-Driven Development of Next-Generation Vertical GaN Power Devices | Marc Gensch, Fraunhofer ISIT |
| 11:00 AM | Silicon’s Enduring Edge: Advanced SuperQ Power Device Development and Interface Trap Extraction Using SILVACO TCAD | Stan Soloviev, Ideal Semiconductor |
| 11:30 AM | Using Victory 3D Simulation in 375V Partial SOI SJ LDNMOS Breakdown Voltage Study | Dr. Elizabeth Kho Ching Tee, X-FAB |
Agenda subject to change.
Walden C. Rhines, Ph.D., has served as our Chief Executive Officer since August 2025, and as a member of our board of directors since September 2022. From March 2020 to June 2025, Dr. Rhines served as President and Chief Executive Officer of Cornami, Inc., a fabless semiconductor company. Since 2015, Dr. Rhines has also served as a member of the board of directors and as chair of the compensation committee of Qorvo, Inc. (Nasdaq: QRVO), a semiconductor company, since January 2015 and its chairman since November 2023. He served as a member of the board of directors of PTK Acquisition Corp. (NYSE: PTK), a special purpose acquisition company from July 2020 until September 2021 and served on its audit, nominating and compensation committees. From October 1993 to March 2017, Dr. Rhines served as President and Chief Executive Officer of Mentor Graphics Corporation, an EDA company, and chairman of its board of directors from 2000 until its acquisition by Siemens in March 2017, pursuant to which the company was renamed Mentor Graphics, a Siemens Business. Following the acquisition, Dr. Rhines served as President and Chief Executive Officer of Siemens EDA (formerly Mentor Graphics, a Siemens Business), from March 2017 to October 2018, after which he served as its Chief Executive Officer Emeritus until September 2020. Dr. Rhines received a B.S.E. in metallurgical engineering from the University of Michigan, an M.S. and Ph.D. in materials science and engineering from Stanford University, and a M.B.A. from the Southern Methodist University, Cox School of Business.
Dr. Walden Rhines, our new CEO and EDA industry luminary, will share his motivation in joining Silvaco with a backdrop of rapidly increasing complexity in advanced semiconductor process, design and the need for a quantum leap in engineering productivity. He will provide thoughts on how artificial intelligence will transform semiconductor design and manufacturing workflows and the effects upon traditional development approaches.
In this talk, we will explore the pivotal role of memory innovations in driving the AI revolution, highlighting how advancements in DRAM, NAND, and high-bandwidth memory are enabling unprecedented growth in compute capabilities. The exponential and super-exponential increases in data and memory demands fueled by AI applications will be discussed, including the shift in compute architecture towards GPU-centric systems, and the critical importance of performance, capacity, and energy efficiency in memory technologies.
The speaker outlines the transition from planar to 3D memory structures, the integration of novel materials, and the adoption of advanced packaging techniques to meet future requirements. Emphasis is placed on the necessity of AI-driven modeling and digital twins to accelerate chip development, manage complexity, and optimize fab operations, underscoring the need for ecosystem collaboration to sustain innovation and address the challenges of next-generation memory and compute solutions.
Gurtej Sandhu is Principal Fellow and Corporate Vice President at Micron Technology. In his current role, he is responsible for Micron’s end-to-end (Si-to-Package) R&D technology roadmaps. The scope includes driving cross-functional alignment across various departments and business units to proactively identifytechnology gaps and ensure resourcing to execute on developing technology solutions. The responsibilities include driving state of the art methodologies to help develop complex technologies faster and more efficiently which entails managing Data and Domain modeling organizations to resource and execute on developing innovative tools for future memory scaling. Dr. Sandhu’s responsibilities also include managing interactions with research consortia around the world.
At Micron, Dr. Sandhu has held several engineering and management roles. He has been actively involved with a broad range of process technologies for IC processing and has pioneered several process technologies currently employed in mainstream semiconductor chip manufacturing.
Dr. Sandhu received a degree in Electrical Engineering at the Indian Institute of Technology, New Delhi, and a Ph.D. in Physics at the University of North Carolina, Chapel Hill, in 1990. He is a Fellow of IEEE and recognized as one of the top inventors in the world. In 2018, he received the IEEE Andrew S. Grove Award for outstanding contributions to silicon CMOS process technology that enables DRAM and NAND memory chip scaling.
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Power Devices, and specifically Wide bandgap (WBG) power devices are rapidly expanding into new, high-growth applications—from electrified transportation and renewable energy to AI data centers operating at megawatt scale power densities. This presentation examines how next-generation power technologies are being enabled by a shift from empirically heavy development toward simulation and AI driven workflows. Using examples across Si, SiC, GaN, and emerging materials, we show how TCAD-based design at scale supports faster calibration, device optimization, and manufacturing readiness as application requirements diversify and accelerate.
The talk introduces Silvaco’s AI powered Fab Technology Co-Optimization (FTCO™) approach, which combines simulation at scale, smart DOE, and machine learning surrogate models to create physics based digital twins of devices and processes. Through case studies—including pGaN HEMTs, vertical GaN, and SiC DMOS technologies—we demonstrate how calibrated TCAD models and ML surrogates enable rapid optimization, variability analysis, and yield prediction while significantly reducing development cycles and physical DOE cost. Attendees will gain practical insight into how digital twins and parallel simulation workflows are transforming power device design, from early technology pathfinding through manufacturing support and application level validation.
Britt has been at Silvaco since November 2024. He is an FAE for Power devices. Britt started his career at Texas Instruments and was a compact modeling engineer for 25+ years and an IC modeling engineer working as factory support for the FAE teams for 6 years. He was the first chairman of the Compact Model Council (now Coalition) for 7 years. Britt came to Silvaco after 4 years at Wolfspeed in the R&D team, working on scaling and predictive modeling of SiC Power MOSFETs. Additional support activities for internal corner modeling and external modeling questions for both discrete and module products were also his responsibility.
Next generation vertical GaN devices show great promise in increasing power delivery for electric vehicles, AI datacenters, and renewable energy infrastructure. In this presentation, Fraunhofer ISIT will discuss advancements in vertical GaN power device technology, with a special focus on the pivotal role of Silvaco Victory TCAD in the innovation process. As the demand for higher efficiency and current density in power electronics grows, physics base simulation workflows enable researchers to accurately model and optimize device structures, material properties, and process parameters before fabrication. This approach streamlines the development cycle, reduces costly iterations, and enhances device reliability by allowing for virtual prototyping of complex vertical GaN architectures. Ultimately, simulation serves as a bridge between theory and practical implementation, driving the successful realization of next-generation vertical GaN devices for high-performance applications.
Marc Gensch is a Research Associate and Project Leader at Fraunhofer ISIT within the Advanced Devices Group. He holds a B.Sc. and M.Sc. in Physics from the University of Hamburg and earned his doctorate at the Technical University of Munich in cooperation with DESY. Marc’s work focuses on integrating ferroelectric AlScN layers into innovative device architectures, as well as advancing GaN HEMT and vertical GaN device development. At Fraunhofer ISIT, he leads projects such as VerGaN and PowerCare and contributes to initiatives like NeuroSmart & Scaling and APECS, driving progress in next-generation semiconductor technologies.
Despite ongoing predictions that wide-bandgap materials will soon eclipse silicon in power device applications, silicon continues to demonstrate remarkable innovation and staying power in the semiconductor industry. As highlighted in the recent article “Reports of Silicon’s Death Have Been Greatly Exaggerated,” new technological advances in silicon device architectures—such as SuperQ Technology—are enabling unprecedented cost and performance improvements, outpacing legacy designs while leveraging the vast experience and infrastructure established for silicon processing. This enduring relevance underscores the motivation for our work: applying advanced TCAD methodologies to push the limits of silicon power device performance.
In this study, the SILVACO TCAD platform—including Victory Process, Victory Device, Victory DOE, Victory Analytica, and Mixed-Mode Simulation—was leveraged to accelerate the design and in-depth modeling of SuperQ-based silicon power devices. The focus was on test diode structures with deep trenchs, where accurate matching of simulated and experimental capacitance-voltage (C–V), conductance-voltage (G–V), and current-voltage (I–V) curves was essential for extracting interface trap distribution parameters along the trench sidewalls. The iterative workflow made intensive use of Victory DOE and Analytica modules: DOE facilitated systematic simulation of key process and physical parameters, while Analytica enabled statistical analysis and multi-dimensional data mining, leading to the best-fit parameter sets for trap distributions.
Mix-Mode Simulation was employed to directly model dynamic and steady-state characteristics under realistic boundary conditions. The result was a robust methodology that resolved key discrepancies between modeled and measured C–V, G–V, and I–V behavior, providing crucial insights into interface physics and charge dynamics in next-generation devices.
This work underscores the critical role of SILVACO’s integrated simulation and analytics suite in advancing silicon power device design, reducing development cycles, and enabling physically guided optimization of complex device architectures.
Stanislav I. Soloviev, PhD, is a Senior Device Engineer specializing in semiconductor device design, process integration, and material characterization. He has significantly advanced charge-balanced structures and edge termination techniques for high-voltage power devices. His expertise encompasses failure mode effects analysis, root-cause identification, and yield improvement in high-volume manufacturing. Dr. Soloviev earned his PhD in Electrical Engineering from Taganrog Institute of Technology and has authored over 50 peer-reviewed publications and holds 10 patents
Building on our earlier demonstration of combining partial SOI and SJ technologies to create a highly effective high-voltage LDMOS platform, new challenges arise at operating voltage goes to 375 V. At these higher voltages, device performance becomes significantly more sensitive to the handle-wafer diode potential, and conventional 2D, repeatable termination structures are no longer sufficient, as confirmed by experimental results.
To overcome these limitations, we developed a completely new 3D termination architecture. Using advanced 3D TCAD, we identified out-of-plane electric-field crowding caused by 90-degree bending of potential lines toward the device midpoint, leading to termination hot-spots. Addressing this required full 3D physical modeling; however, the device size, deep-trench isolation geometry, floating silicon regions, and extensive silicon/oxide interfaces made standard full-domain 3D simulation impractical. A novel domain-decomposition methodology using Silvaco Victory 3D TCAD finally tackle this issue. The device is partitioned into smaller sub-domains, enabling accurate Monte Carlo implantation and physical annealing simulations. These process-simulated elements are subsequently merged and re-meshed for complete 3D device simulation, allowing accurate representation of the complex termination structure and successful optimization to breakdown voltage of 460 V.
Dr. Elizabeth Kho Ching Tee has nearly two decades of experience in power semiconductor device research and development. She has led major advancements in Superjunction and partial SOI technologies and contributed to the development of integrated power devices, including lateral IGBTs, RESURF LDMOS, and Superjunction LDMOS on PSOI. More recently, she has expanded her work into SiC MOS devices. Dr Elizabeth holds five patents and has authored 18 publications in leading journals and conferences.
Developing a comprehensive foundation IP portfolio around a new PDK is a non-trivial effort, often trivialized. Building the proper inventory of standard cells is the first step. Optimization for power, area, and performance requires careful planning and trade-offs. VT selection, track heights, and process corners all play vital roles. Bit cells, memory architectures, arrays, speed, and density each have selection criteria that are equally critical to the robustness of a process portfolio.
In this presentation, I will step through a proven methodology that has enabled many customers to navigate from a preliminary PDK release to first-silicon success.
Keith brings over 30 years of systems-level semiconductor experience to the organization. He leads platform definition and development strategy as part of the leadership team.
Before joining Silvaco, Keith held senior leadership roles at indie Semiconductor, Ambiq Micro, Cirrus Logic, and Silicon Laboratories. Keith earned a BSEE from UT Austin’s Cockrell School of Engineering and holds six US patents.
CellForge 2D from Silvaco is an interactive layout DRC cleanup and optimization tool enabling migration of standard cell layouts between cell architectures that share similar routing structures. With the unique capability of the cell template and rules definitions, standard cells can be migrated from one architecture to another architecture within the same technology node as well as from another technology node. With its powerful layout cleanup engine, layout is rendered DRC clean and helps layout optimization. Design rules for layout patterns involving Poly (gate) geometry restriction, contacts, vias, active regions, jogs are optimized for a given initial layout either migrated from another architecture or simply from a different track height. It supports advanced lithography patterning and design constraints flexibility to customize the layout design rules flow through TCL scripting API. Integration with signoff/layout editing environments for LVS, DRC, abutment checks, and extraction flows.
Using Silvaco’s CellForge 2D, GlobalFoundries was able to save weeks migrating a 130nm standard cell layout library from short gate length, low voltage (LV) cells library to large, asymmetric gate length high voltage (HV) cells. The tool enabled optimization of redundant contacts, conflict resolution with interactive transistor width, contact placements and poly gate adjustments with cell width. With its DRC-correcting automation and scaling scripts, CellForge 2D saves both the time and tedium involved migrating cells from one technology to another, and one architecture to another. In another application of CellForge 2D, standard cell track migration is achieved seamlessly saving layout design time.
Navneet Jain is a Distinguished Member Technical Staff at GlobalFoundries, Inc, Santa Clara, since 2009. He holds a PhD and MTech in EE form IIT Delhi, India and BE(Hons) in EEE from BITS Pilani, India. He has over 25 years of experience in the field of circuit/logic design, optimization and methodologies for timing closures for microprocessors and graphics chip design at SGI, Transmeta, AMD, SGI, Software &Technologies (Duet) and Center for Applied Research in Electronics (CARE) at IIT Delhi. At GlobalFoundries he has architected and productized standard cells libraries in 22FDX, 12LPP, 45SPCLO, RF SOI, Bulk CMOS, and SiGe including several test chips for FAB silicon validations with emphasis on developing ultra-lower and low leakage design. Navneet has over 30 patents and 10 publications in IEEE transactions and international conferences. He is designated as Master Inventor and also a recipient of the CEO award at GlobalFoundries
The AI age creates many new challenges for Automatic Test Equipment (ATE) suppliers. One such challenge relates to emerging high-speed PHY optimized for ultra-low pJ/bit and short haul, both standards-based and proprietary. These emerging PHY requirements challenge traditional ATE capability development by requiring ASIC solutions with much faster Time-to-Market (TTM) that tolerate larger market value uncertainty. Teradyne is meeting this challenge with an optimized ASIC development model and system architecture that provides much faster time to market with modest investment for emerging PHY needs. The first such effort was implemented last year and delivered a silicon prototype proof of concept demonstrating less than 1 year TTM for high-speed PHY ATE capability with modest investment and predictable schedule, leading to customer delight, thought leadership credit, and strategic partnerships.
A key part of this ASIC development model is reliance on best-in-class IP providers. Mixel’s history of first pass successes and our long-term partnership gave Teradyne the confidence to tape out with the latest generation of Mixel’s MIPI C-PHY/D-PHY Combo Universal IP without waiting for test silicon proof of this IP. This was a very good bet that contributed to a great strategic business outcome for Teradyne.
With over 25 years of experience in the Semiconductor and Automatic Test Equipment (ATE) industries, Jason Messier is a seasoned technologist currently serving as Director of Silicon Strategy and Technology at Teradyne. Recognized for his transparent leadership style and passion for technically elegant solutions to emerging market needs, Jason contributes thought leadership through identification, organizational championship, and product ownership of novel ATE concepts and initiatives. Previous roles at Analog Devices, Intersil, and semiconductor startups reflect deep experience in product definition, mixed-signal IC design, and customer-focused solutions, leading to multiple successful well-differentiated product launches. Jason holds a BSEE from Northeastern, an MSEE from Carnegie Mellon University, and an MBA from Babson College.
As DRAM layout design continues to shrink, Process Proximity Correction(PPC) faces the challenge of generating manufacturable masks with high yield while satisfying stringent mask rule constraints. Traditional Manhattan-based mask geometries are becoming increasingly restrictive and ineffective at advanced nodes. To address these limitations, we have evaluated and implemented a curvilinear OPC solution using Silvaco’s DimensionPPC. DimensionPPC provides the functions needed to achieve curvilinear OPC solutions, including curvilinear mask synthesis and optimization(PPC), simulation‑based verification (PPV), and curvilinear mask rule check(MRC). We will present the differences between conventional and curvilinear OPC, as well as several DRAM layers where curvilinear OPC has been successfully applied and the resulting benefits.
N. Kosa received a Bachelor of Science in Electrical Engineering from the University of California, Davis, in 1996. She joined NEC in 1996 as a photo engineer. In 2000, she transferred to Elpida Memory Inc. In 2014, she joined Micron Memory Japan and began working on OPC. She is currently a Member of Technical Staff in the Advanced Mask Development, Recipe, and Tool Development team.
Semiconductor and photonics R&D utilize multi-physics-based TCAD tools to virtually prototype new technologies. Once this technology reaches the manufacturing stage, optimization requires expensive Design of Experiments on wafers. Production teams often request simulation assistance from R&D when technology issues arise, but the process can be slow and limited by the availability of simulation expertise. Silvaco’s Fab Technology Co-Optimization (FTCO™) is an AI/ML-driven solution resulting in physics-based digital twin models. This approach integrates the expertise of the simulation R&D engineer into the fabrication process via the physics-based Digital Twin, enabling manufacturing engineers to conduct what-if analysis and address questions more efficiently.
Garrett Schlenvogt, Ph.D., has been Vice President of Worldwide Field Applications Engineering since 2024, overseeing global FAE operations, including technical presales and support. Previously, he served as Director of Worldwide Field Applications Engineering. Since joining Silvaco in 2013, he has held various leadership positions and led research collaborations with academic and commercial institutions. Before Silvaco, he researched radiation and reliability simulation of CMOS technologies for implantable medical devices. Dr. Schlenvogt earned his BSE, MS, and Ph.D. in Electrical Engineering from Arizona State University.
In the semiconductor industry, precision in design and control in manufacturing are essential for innovation, efficiency, and yield. In this talk, we highlight some of Dassault Systems’ capabilities to sustain and accelerate semiconductor manufacturing innovation. This includes among other things, fluid flow simulations to assess particle transport and contamination risks inside Fabs; plasma simulations for etching and deposition to optimize material removal and material growth processes; deformation analysis during wafer cleaning to prevent breakage and defects; and chemical mechanical planarization (CMP) simulations to ensure surface uniformity. Powered by the 3DEXPERIENCE® platform, these solutions deliver an end-to-end virtual environment that reduces variability, improves yield and device performance, and uniquely closes the design to manufacturing loop through continuous, data driven feedback and rapid process optimization.
Emmanuel Leroux is leading the EDA (Electronic Design Automation) strategy for the Simulation Brand (SIMULIA) at Dassault Systèmes. His job, with his Team, is to propose R&D, Partnership to meet a 3Y/6Ytarget for Multi-domain / Multi-scale MODeling and SIMulation (MODSIM) in Electronics involving also manufacturing process simulation. His responsibility includes also more tactical steps and guidance of Go-To-Market and Marketing for the simulation of Semiconductors and PCB (Printed Circuit Boards). Emmanuel received his Ph.D in Electronics in 1998 at University of Lille in France working together with Politecnico di Torino in Italy. In 1994, he joined High Design Technology (Torino) as a PCB Signal Integrity Applications Engineer. In 2020 he joined Computer Simulation Technology (CST), first as Application Engineer (Darmstadt, Germany) and then opening the CST office in Italy. From 2005 he was CST Country Manager for the Southern East Mediterranean area. After the acquisition of CST by Dassault Systèmes in 2016, he led the multi-domain simulation technical/sales Team in that same area. In 2021, he joined Dassault Systèmes SOLIDWORKS Team with the responsibility to launch the Electromagnetic simulation business within SOLIDWORKS resellers at Worldwide level. With his new position Emmanuel has the ambition to plug in EDA MODSIM into a PLM/MBSE/Generative AI framework.
Morteza Mohseni works at Dassault Systèmes SIMULIA as a Roles Portfolio Manager, where he coordinates and contributes to R&D, go-to-market strategy, marketing, and partnership activities to engineer and evolve the SIMULIA brand portfolio within Dassault Systèmes. In this role, he helps to ensure tailored value delivery for semiconductor customers and communities by leveraging market intelligence, close customer engagement, and strategic collaborations. His work supports SIMULIA’s growth objectives, with a particular focus on High-Tech industries and applications in the electronics domain, primarily semiconductors.
He received his PhD from TU Kaiserslautern, Germany, where he worked on the design, simulation, fabrication, and characterization of spintronic-based RF integrated circuits (ICs) and magnetic memories for data processing and data storage systems. He has co-authored more than 30 publications in peer-reviewed journals in the fields of device and applied physics. After a short period of research focused on hardware design for hybrid semiconductor devices for data processing and quantum computing, he transitioned into industry, joining Dassault Systèmes to bridge advanced research with industrial simulation and design workflows.
As Moore’s Law pushing semiconductor technology forward, transistor architectures have entered the three-dimensional era. While FinFETs have long dominated advanced nodes, the sub-3nm era also features Gate-All-Around (GAA) nanosheet transistors, enabling continued scaling. This SURGE talk presents a comprehensive workflow for modeling and simulating these cutting-edge devices using Silvaco Victory TCAD.
We focus on key physical effects and models critical for accurate device representation, including quantum confinement, band structure corrections, strain engineering, and mobility degradation. Powered by Silvaco Victory Device, we demonstrate how simulations can be calibrated and validated against experimental data. Finally, we show how Victory Analytics and Fab Technology Co-Optimization (FTCO™) enable multi-dimensional process-design exploration, accelerating device development, improving yield, and optimizing process windows for next-generation high-performance, low-power logic ICs.
Zhenhua Wu is a professor with the Zhejiang University. He received his Ph.D. degree in Chinese Academy of Sciences, Beijing, China, in 2011. He joined Semiconductor Research and Development Center, Samsung Electronics, Suwon, South Korea, from 2011 to 2016, and then joined the Institute of Microelectronics, Chinese Academy of Sciences. In 2024, he joined the Center for quantum matters, Zhejiang University, Hangzhou, China. His current research interests include advanced semiconductor manufacturing technology, quantum transport simulation of nanoscale transistors and AI-Augmented TCAD simulation method. His works have been published in IEEE EDL/TED, PRL/PRB/PRApplied, APL/JAP, Nat.Mat/Comm etc., or presented EDTM/SISPAD/IEDM/VLSI etc., conferences. In 2024, He was listed among Elsevier’s top-2 % scientists worldwide.