Accelerate the Circuit Simulation Flow with Jivaro Parasitic Reduction
Jivaro is a unique, stand-alone solution for the reduction of parasitic networks that include resistors, capacitors, and inductors (RLCK). It helps back-end verification teams (SPICE or FastSpice users) speed up post-layout simulation of huge extracted parasitic circuits, while keeping high accuracy of results.
Jivaro offers a complete set of features to manage the reduction process while controlling accuracy. Out of the box, the operation of Jivaro is direct and simple, and the basic reduction features meets the expectations of most designers. To further increase simulation speed while maintaining the same accuracy, advanced features are required to reduce the complexity of the parasitic networks.
After a short introduction of Jivaro, a methodology to improve your simulation flow will be shown, identifying the necessary features and controls to do advanced netlist reduction.
What attendees will learn:
- Reduce R, C, L extracted netlist to speed-up SPICE simulation while keeping high accuracy levels
- Methodology to improve the impact of Jivaro on simulation performance
Presenter
Mr. Simon-Alexis Abric is a Corporate Application Engineer for Silvaco France. He is responsible for customer technical support for reduction (Jivaro) and parasitic analysis (Alps) products. Prior to Silvaco, he was an Application Engineer at Edxact SA for four years.
Mr. Abric earned a Master of Engineering degree in integrated circuits and systems in 2013 from the engineering school ENSEIRB in Bordeaux, France.
When: January 16, 2020
Where: Online
Time: 10:00am-11:00am – (PST)
Language: English
WHO SHOULD ATTEND:
Anyone who works with post-layout netlists and uses parasitic extraction; engineers seeing their simulations deeply impacted after layout extraction and looking for a solution to improve run-times; analog and digital designers; CAD and PDK engineers.