Model Extraction Flow with Utmost IV for Vertically Stacked Nanosheets Using the Leti-NSP Model
Leti-NSP is an innovative model for advanced multi-gate MOSFETs. The model covers state-of-the art devices such as vertically stacked or vertical channel nanosheet/nanowires and FinFETs. In this webinar we will present a parameter extraction methodology for Vertically Stacked Nanosheets, based on this model. The extraction flow has been implemented in the Silvaco Utmost IV modeling software. We will illustrate the extraction flow step by step, emphasizing the particularities of its implementation in Utmost IV. Both the Verilog-A version of the model as well as the built-in model implementation in the Silvaco SmartSpice circuit simulator will be covered.
What attendees will learn:
- Extraction of SPICE Model parameters for Vertically Stacked Nanosheets using the Leti-NSP model
- Step-by-step illustration of the extraction flow implemented in Utmost IV
- Comparison between the Verilog-A and the built-in version of the Leti-NSP model
Presenter
Dr. Bogdan Tudor is head of Silvaco’s Device Characterization Group. He is responsible for all aspects of the Device Characterization Group’s activities, including R&D, field operations, and modeling services. He has 15+ year experience in EDA and SPICE modeling fields with extensive expertise in Device characterization, Compact Model development, MOSFET Aging Reliability Analysis, and Software development. Dr. Tudor holds a M.Sc. in Electrical Engineering and a Ph.D. in Microelectronics from the Polytechnic University in Bucharest, Romania.
WHO SHOULD ATTEND:
Engineers, management and academics, who are interested in SPICE modeling methodologies for advanced MOSFET devices, such as Nanosheets, in Verilog-A-based model extraction, and in SPICE model extraction and optimization, in general
When: July 30, 2020
Where: Online
Time: 10:00am-10:30am-(PDT)
Language: English