Singular Point Source MOS Cell Concept (S-MOS) Implemented on a Narrow Mesa Trench IGBT

Acknowledgment

This paper was first printed in the Proceedings of 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2021 doi: 10.23919/ISPSD50666.2021.9452228.

Abstract— A Singular Point Source MOS (S-MOS) cell concept suitable for power MOS based devices is presented. The S-MOS differs from a standard Planar or Trench MOS cell in the manner by which the total channel width per device area is devised. The S-MOS single cell channel width is defined as the peripheral length of a line running approximately along the N++ source and P channel junction which is positioned on a gated trench side-wall. The length of the line is established from a singular point implant source for forming the N++ source region which geometrically corresponds to the shape of the N++/P junction. The N++ and PChannel profiles achieved are similar to those for a planar cell, but for the S-MOS, they are situated on a trench side-wall. The total device channel width will therefore depend on the total number of gated trench side-walls per chip. The S-MOS provides a unique approach for MOS cell layout designs and is applicable to different MOS based power devices. In this paper, the S-MOS is implemented on a 1200V IGBT by means of 3D-TCAD simulations while providing results highlighting the potential advantages with respect to the device static and dynamic performance. Keywords – MOS cell, Insulated gate bipolar transistors.

INTRODUCTION

MOS cell process/design platforms were developed over the years enabling advanced silicon-based power devices such as the power MOSFET and the Insulated Gate-Bipolar Transistor (IGBT). Both devices have been based on planar or trench MOS cells with a continuous development trend toward cell iniaturization. This led to clear improvements in the overall performance for such devices. On another development front with respect to wide bandgap semiconductors such as Silicon Carbide, the advances made on silicon-based MOS devices have provided a strong base for developing SiC power MOSFETs and IGBTs.

For power SiC MOSFETs, high cell packing densities are essential. Advanced 3D design concepts have been proposed [1] similar to the low voltage FINFET cell structure [2] as they rely on multi-dimensional channel width arrangements for increasing the cell density and reducing the on-state resistance Rdson. On the silicon IGBT front, since the landmark paper by Nakagawa in 2006 [3] along with advanced photolithography process capabilities, low loss 600V and 1200V Narrow Mesa trench NM-IGBT designs have been developed with Trench Mesa dimensions below 1μm for achieving significantly lower on-state losses [4] [5]. Further developments to further optimize these structures are underway especially with respect to the separation regions between active trench cells for improving the blocking capability, switching controllability and robustness [6]. In line with these development trends, this paper presents the “Singular Point Source” MOS cell concept (S-MOS) having distinctive 3D design features for defining and thus adjusting the total channel width Wch (also referred to as channel area) while at the same time enabling higher MOS cell packing densities. The S-MOS concept can be implemented on MOSFETs and IGBTs with the potential to provide improved switching performance while matching the best-in-class conduction losses. In this paper, the S-MOS is demonstrated by means of 3D-TCAD simulations on 1200V IGBTs and compared to narrow mesa trench IGBTs.