• Simulation Standard Technical Journal

Simulation Standard

Technical Journal

A Journal for Process and Device Engineers

Mixed-Signal Simulation with SmartSpice in the Cadence Design Framework II

Users of the Cadence Design Framework II (DFII, versions 4.4.0 and above) have been enjoying a tight integration between SmartSpice and the Analog Artist Electrical Design System and Composer Design Entry tools. This integration is achieved via the Cadence Spice Socket (cdsSpice) and the Open Analog Simulation Integration Socket (OASIS). It has been comprehensively documented in previous issues of the Simulation Standard, and also in a new application note (Ref No. SS/99-2).

Intrinsic Capacitance Parameter Extraction in UTMOST III

The intrinsic capacitance parameter extraction routine (INTCAP) is in the CAP analysis section of the UTMOST III MOS module (Routine#67). The INTCAP routine has 5 different intrinsic cap measurements and a "simulation only" capability for all intrinsic caps. Recent developments have improved the INTCAP routine. Users should have UTMOST III MOS module version 15.2.0 or higher to be able use the examples and explanations presented in this article. The INTCAP routine allows users to measure the MOS capacitances when the device is under DC bias and conducting current.

Hints & Tips March 1999

Q: I often use the temporary reference point, but I would like to see both absolute coordinates and relative coordinates, without toggling the reference point on and off.

Advanced Pairwise Merging Algorithm for VLSI Floorplanning

This paper concerns the problem of determining optimal placement of rectangular blocks within a rectangular area known as the packing or cutting-stock problem. This problem arises at then floorplanning stage of VLSI design.

Introducing Guardian – LVS Verification for PC-based Platforms

Guardian is a (state-of-the-art) hierarchical netlist comparison system, which eliminates many of the disadvantages of existing programs. Running on PCs under Windows NT, it easily compares circuits with a large number of devices. The advanced algorithms implemented in Guardian allow a substantial reduction of execution time and also detect discrepancies between two netlists more precisely. Guardian generates a comprehensive hierarchical report, which is easy to read. An embedded tool, called the Spice Netlist Rover, links report files with source netlists to make inspecting correct matches and errors simple.

Mixed Circuit Device Simulation of Single Event Upset in a Memory Cell

This article presents Single Event Upset (SEU) simulation of a SRAM cell using MixedMode3D. MixedMode3D provides the capability to simultaneously perform circuit simulation coupled with three-dimensional device simulation. This allows one to examine the internal operation of a three-dimensional numerically simulated device and predict the response of the attached circuit in a self consistent manner.