Reducing the Layout Development Cycle Time for Standard Cells at STMicroelectronics
As the semiconductor industry is evolving, product turnaround time must be reduced while ensuring high quality, reliability, and profitability. This requirement translates to the reduction of standard cell layout development cycle time without compromising robustness, density, and manufacturability of the integrated circuits that are produced.
The presenters introduce the Cello platform for creating and optimizing standard cell libraries. It includes a layout optimization engine, a built-in Tcl interpreter with a scripting API, distributed jobs support, and export of backend views. Starting from layout creation from the schematic, it can ease the designer’s life for improvement, migration, and validation of cell layouts. These features are easily integrable inside the conventional layout development framework and enable layout engineers to design standard cell layouts faster.
In this webinar, Sharmistha Sinha and Anand Mishra share their analysis and experience with Cello done at ST on multiple technologies. Based on this study, they identified the scope to improve the overall efficiency of standard cell development. The results showed effort savings of approximately 40% by using Cello for the development of layouts from start to finish.