Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors

Domenico Palumbo, Silvia Masala, Paolo Tassini, Alfredo Rubino, and Dario della Sala
Copyright © 2007 IEEE.

Reprinted from IEEE Transactions on Electron Devices, VOL 54, NO 3, March 2007.

Abstract

This paper is focused on the stability of n-channel laser-crystallized polysilicon thin-film transistors (TFTs) submitted to a hydrogenation process during the fabrication and with small grains dimension.With the aid of numerical simulations, we investigate the effects of static stress using two types of procedures: the on stress and the hot carrier stress. Results show that the variations of trap state density into the whole polysilicon layer and not only near the drain junction are responsible for the degradation of TFTs performances in both the two types of stress and that the interface trap states play a negligible role compared to the bulk trap states.

Index Terms—Density-of-states (DoS), fixed charge, numerical simulation, reliability, thin-film transistor (TFTs).

I. Introduction

LASER-CRYSTALLIZED polycrystalline silicon thin-film transistors (TFTs), processed at a low temperature (below 600 oC), are devices of great importance in the microelectronics industry since they are currently widely used in active-matrix liquid crystal displays and are suitable for the emerging activematrix organic light emitting displays (AMOLED) [1].

By using low laser energy densities up to 200 mJ/cm2, we have fabricated devices with small grains dimension with a mobility of up to about 3 cm2/V . s. These n-TFTs are suitable not only to drive an OLED diode [1], [2] but also to realize the row drivers [3]; moreover, the increased uniformity of electrical parameters, compared to large grains size TFTs, gives rise to a reduction, for instance, of the threshold voltage spreading [4], avoiding more complicated pixel circuit to overcome this problem [5], [6] and obtaining brightness uniformity over large areas.

Their drawback is the instability after electrical stress [7], [8], due to a high density of in-grain and grain boundary defects, to poor properties of the gate insulator and to poor polysilicon/ oxide interface [9].

The purpose of this paper is to understand which are the main mechanisms originating from device degradation under a bias stress. This is accomplished by comparing the computer simulation of device characteristics with the experimental data.