Circuit Verification via Hypergraph Realization

One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to test the consistency between the actual circuit, represented by the layout, and the nominal circuit upon which the design was based.

HINTS & TIPS – March 1998

Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?

3D Simulation of Power Devices Using Giga3D and MixedMode3D

Recent additions to the ATLAS device simulation framework have added the ability to simulate 3D electrothermal effects in Giga3D and mixed circuit simulation with 3D device simulation in MixedMode3D. The new modules add to the existing 3D device simulation within ATLAS as shown in Figure 1.

MixedMode Simulation of Power Electronic Converters

With mounting concern for energy conservation and nature preservation, power electronics is becoming increasingly dominant in everyday life.

Polysilicon Gate Depletion Effects in Sub-Micron MOSFETs

It is usually assumed that the poly gate in a MOSFET is doped at a concentration such that depletion in the gate either does not occur or that any depletion effects can safely be ignored. This article aims to quantify poly depletion effects for typical sub-micron device dimensions using ATHENA and ATLAS process and device simulators.

Mesh Control in ATHENA Avoiding Problems and What to do If they Occur

Mesh control in process simulators is one of the major issues tackled by any user. Over the years the meshing algorithms with SSuprem4 and ATHENA have been improved to the stage where most arbitrary structures can be solved. New approaches such as automated ADAPTIVEMESH algorithms or standalone programs such as DevEdit exist to help users.

HINTS & TIPS – February 1998

Q: How can external tools be run inside of Silvaco's run-time environment DeckBuild? Is it possible to include UNIX commands along with simulator syntax inside an input file?

The SmartSpice Interface to Cadence (revisited)

The SmartSpice interface to the Cadence Design Framework II has been substantially improved in its latest release (version 1.0.8.R), following feedback from a number of existing users.

CellRATER from Taveren Technology fast, Accurate Cell Library Characterization for Deep Submicron Timing Flow Improvement

Taveren Technology, Inc., a startup company based in Austin, Texas is busy developing the next generation performance characterization tool suite.

Cell Characterization with .MODIF Statement in SmartSpice

SmartSpice provides many unique and powerful features to facilitate parametric analysis in general and cell characterization in particular.