Expert Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as enclosure wires, offset wires and sets of rectangles. Pwire objects enable extremely quick and efficient creation and editing of guard rings and shielded paths which are increasingly important due to higher integration density of IC designs.
Many users would like to extract SPICE models from their process and device simulation using Athena and Atlas to be used in actual circuit simulation without actually fabricating the device.
Using SILVACO’s Utmost you can extract SPICE model parameters from the simulation results of Athena and Atlas.
For LCD and Memory designs, Array Copy function on Gateway is conveniently used. Users may want to align instances from specified instance number, for example starting from X100 or X1000. Here introduces a convenience way to realize it.
A new Hierarchical Layout versus Schematic (HLVS) system that provides significant improvement in verification of huge circuits is described. Other of LVS verification tools perform a netlist flattening and comparison in transistor level [1, 2]. These tools are based on standard graph isomorphism algorithms and are sufficiently efficient in practice.
Introduction
One of the key components in many RF ICs applications is the inductor. It is very important that the inductor has optimal design, meaning optimal geometry with the best possible characteristics [1]. Our computer-aided optimization technique using geometric programming (GP) has been used to find the optimum design for spiral inductors with different layout [2-4]. The goal is selection of the best geometry of inductors to find optimal values of inductor parameters (the number of turns and layout dimensions) and then drawing layouts of optimal inductors. Silvaco Expert is a powerful tool for drawing spiral inductors with different mask geometry (square, octagonal or circular). In this paper we presents a simple way to draw layouts of optimal inductors in Expert, without using parameterized cells.
Q: When I do an extract, the generated layers are present in the layout. If I need to do layout modifications I find it very cumbersome to deal with the generated layers. Is there a way to turn-off all of the generated layers so that layout modifications can be done without them cluttering things?
Hipex-NET uses two techniques to calculate resistor values. First method of resistance extraction, which is usual for full chip netlist extractors and uses heuristic algorithms to recognize common shapes for which were obtained empirical formulas depending on geometry of resistor body and resistor terminals. Unfortunately, this method doesn’t cover the wide range of resistors and can handle only rectangular resistors, L-bends, and T-shaped resistive fragments. It also can be used to calculate resistance of snake and dog-bone shapes. We should also note that comparing to Maverick, Hipex-NET recognizes some new shapes as routine shapes for which resistance value can be calculated by the well-known formulas [1].
Introduction
Mercury cadmium telluride (HgCdTe) is a semiconductor material whose material properties are adjustable through altering its constitutive molar fractions. HgCdTe has found extensive use in optical detection, and in particular found wide use in infrared photodetectors over the past few decades. Applications in this area have been the main driving force for research on this material and for a good review see [1].
III-Nitrides have recently attracted attention as a promising material class for high-power, high-frequency microelectronic applications at elevated temperatures. They possess large band gaps, relatively small effective masses in the conduction band minimum, large offsets to the conduction band satellite valleys, and high polar optical phonon frequencies. The large band gaps provide high-breakdown field strengths, while the other basic physical properties result in high low-field mobilities and high saturation velocities.
We describe here two approaches to model the quantum effects that can no more be neglected in actual and future devices. These models are the Schrödinger-Poisson and Density-Gradient methods fully integrated in the device simulator ATLAS. Simulations based on such methods are compared to each other on electron concentration and C-V curves in a MOS-capacitor.