Electrically Controlled Silicon-based Photonic Crystal Chromatic Dispersion Compensator with Ultra Low Power Consumption

We show full 3-Dimensional (3D) electrical and optical simulation of a tunable silicon-based Photonic Crystal (PhC) Chromatic Dispersion Compensator (CDC) with high power efficiency and ultra-low power consumption (114nW), operating at a speed of 40.5MHz. The device exploits a structure where the optical field maximum is not in a PhC waveguide, but rather in a hybrid Si3N4/Si/SiO2 structure that will allow greater ease of fiber coupling due to larger mode size and reduced loss. The CDC is broadband, and produces constant 2nd order chromatic dispersion over an optical communication band such as C-band.

SONOS/SANOS Simulation in ATLAS

Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) Non-Volatile memory structures can be simulated using ATLAS. The basic principle of these devices is the use of a charge trapping Silicon Nitride layer embedded in the oxide layer separating the gate from the channel. This results in an oxide layer between the gate and the Silicon Nitride layer, and another between the Nitride layer and the semiconducting channel (Figure 1). The Silicon Nitride layer can be charged by quantum mechanical tunneling or by hot carrier injection. This results in a shift in the turn-on voltage of the NVM device. The trapped charge can be discharged by quantum mechanical tunneling or by injecting hot carriers of the opposite polarity, thereby erasing the threshold Voltage shift.[1] [2]

Hints, Tips and Solutions – Determining the CV Curve and Terminal Currents of a MOSFET

Q: How can I get a CV curve of a MOSFET? And how can I get the current on all terminals? A: There are two methods to get the CV curve of MOSFET, Small Signal analysis and Large Signal analysis.

Minimization of Well-Proximity Effect by Means of 2D and 3D Monte Carlo Simulation of Retrograde Well Implantation

The formation of deep p- and n- wells using high-energy implantation has become an integral part of CMOS technology process flow. The high energy and high dose implantation into the cleared area of a thick photoresist mask generates retrograde profiles. These profiles have a relatively high peak concentration usually at the depth of approximately 1 micron and a very low surface concentration. From the first glance this process achieves its primary goal to isolate NFETs from PFETs without affecting surface areas where the transistors are formed. Unfortunately for both technology and circuit designers, this relatively simple process step brings about an unwanted Well Proximity Effect (WPE) [1] exhibited by a strong dependence of threshold voltage Vt on transistor location and even orientation within the well.

3D Simulation of Oxidation Induced Stress Using Cartesian Meshes with Adaptive Refinement

The formation of isolation trenches is one of the key process steps used in power device fabrication. Also the intensive scaling of modern semiconductor devices requires significant stress engineering to enhance carrier mobilities and avoid extended defect formation. Simulation results from complex 3D trench and lateral isolation structures are presented together with the inbuilt oxidation induced mechanical stress in the grown oxides. Fast transition of compressive to tensile stresses has been obtained for concave-convex surfaces with internal hydrostatic pressures ranging from 0.04 to –0.04 N/μm2 .

3D Simulation of Ion Milling for Mass Storage Applications

The ion milling process is used extensively in the Hard Disc Drive industry, particularly in the manufacture of thin film magnetic heads. Ion milling is used to pattern many metal and dielectric materials including alloys comprising of Fe, Co and/or Ni transition metals which are commonly found in a thin film magnetic read-write transducers. This paper presents new results for ion milling and redeposition of gold on photoresist patterns at different milling angles and compared with 3D process simulation results.

Self-Heating effect Simulation of GaN HFET Devices – 4H-SiC and Sapphire Substrate Comparison

GaN-based Hetero-Field Effect Transistors have been investigated in high power and high frequency electronics devices. However, such improved performance is still subject to influence of surface and buffer traps. The role and dynamics of traps and their effect on the GaN HFET have already been investigated [1]. In addition to the formation of the 2DEG, an adequate numerical model of device charge control implies proper modulation of the 2DEG in ATLAS [2].

Modeling of GaInP/GaAs DualJunction Solar Cells Including Tunnel Junction

This paper presents research efforts conducted at the IESUPM in the development of an accurate, physically-based solar cell model using the general-purpose ATLAS device simulator by Silvaco. Unlike solar cell models based on a combination of discrete electrical components, this novel model extracts the electrical characteristics of a solar cell based on virtual fabrication of its physical structure, allowing for direct manipulation of materials, dimensions, and dopings. As single junction solar cells simulation was yet achieved, the next step towards advanced simulations of multi-junction cells (MJC) is the simulation of the tunnel diodes, which interconnect the subcells in a monolithic MJC. The first results simulating a Dual-Junction (DJ) GaInP/GaAs solar cells are shown in this paper including a complete Tunnel Junction (TJ) model and the resonant cavity effect occurring in the bottom cell. Simulation and experimental results were compared in order to test the accuracy of the models employed.

Ballistic Quantum Transport in Nanoscale Transistors: a Non Equilibrium Green’s Function Approach

Introduction As MOS field-effect transistors are scaled down to a nanometer regime, quantum effects in both transverse and transport directions start playing a major role in determining device characteristics. In order to address a new challenge, SILVACO has started a deployment of new quantum mechanical models based on Non Equilibrium Green’s Function (NEGF) approach. This is a fully quantum mechanical approach which treats such effects as source-to-drain tunneling, ballistic transport, and quantum confinement on equal footing. The new NEGF solver is suitable to model ballistic quantum transport in such devices as Double Gate or Surround Gate MOSFET, using rectangular or cylindrical geometries in ATLAS. The method used is based on references [1] and [2].

A Novel Approach to Three-Dimensional Semiconductor Process Simulation: Application to Thermal Oxidation

Abstract The paper presents a new approach to three-dimensional semiconductor process simulation that overcomes the problem of moving boundaries and mesh generation. Contrary to using unstructured meshes, the approach makes use of the level set method on fixed Cartesian meshes. A concept of multi-layer structure is introduced to capture an arbitrary complex structure. To handle a big geometrical scale ratio in a structure, the concept of adaptive mesh refinement is used. A special in-house finite-difference scheme is designed to approximate the relevant equations near material interfaces. In the bulk of regular nodes the standard finite difference schemes are used. Application of the approach to the modeling of oxidation of some typical types of structures used in semiconductor technology is demonstrated.