Atomistic Analysis and Next Generation Computing at IEDM 2019

The 65th IEEE International Electron Devices Meeting (IEDM) took place Dec. 9 to 11 at the Hilton San Francisco Union Square.

Here is a very quick summary put together by one of our staff members:

IEDM is THE device conference with more than a thousand participants from major companies and R&D institutes. Many talks were dedicated to new memory devices and circuits, including Ferroelectrics, MRAM, RRAM, driven by the requirements of AI processing. EUV is definitely there for 3nm and beyond. 3D integration was shown for LP-HP logic and RF. Gate-All-Around devices, with nanowires or nanosheets are mature versus FinFET. Novel new interconnect materials will replace Cu-based BEOL. Cryogenic MOSFET devices are being explored for Quantum Computing applications. Power microelectronics technologies in GaN, SiC were included, and new materials like Ga2O3 were mentioned. DTCO is steering device and process simulation. Reliability and variability analysis is now included with new tools. There was little mention of devices made of 2D/TMD materials. Note: Toshiba Memory Corp. is now Kioxia.

Philippe Blaise, senior application engineer for atomistic TCAD from Silvaco France and previously from CEA Leti, presented an invited paper “Ab initio Simulation of Advanced Materials and Devices: Current Challenges”. He discussed the introduction of atomistic simulation tools to semiconductor analysis and described the most promising strategy atomistic tool usage, including the strong link between electronic device variability and atomistic modeling. Simulations of a ferroelectric layer and a resistive RAM (ReRAM) were shown as examples.

At the Silvaco booth in the exhibits area, we presented:

• Co-optimization of power electronics with TCAD
• Simulating 3D stress in flexible substrates with Victory Process 3D
• Optimizing 3D NAND memory select gate with Victory Device 3D
• Silicon nanowire device simulation with Victory Atomistic