Introduction

By default STELLAR calculates the capacitances between interconnect lines and the whole substrate. In certain conditions it may lead to some inaccuracies. For example STELLAR may calculate the capacitance of a poly line over an active area but this capacitance is already present in the spice compact model (Cox). Another example is that the substrate of a MOSFET transistor is usually connected to Vdd or Gnd depending on its polarity.

Polarization-induced charges at the AlGaN/GaN interface of heterojunction field-effect transistors (HFETs) create a high density, two-dimensional electron gas (2DEG) in the channel. One approach to simulating the 2DEG is to place a fixed positive charge at the AlGaN/GaN interface, thus attracting a fixed quantity of electrons to the channel. Silvaco’s ATLAS software can do this with either an INTERFACE statement or automatically with the use of the POLARIZATION parameter on the REGION statement. This is fine, as far as it goes, but this simple approach glosses over some nuances having to do with the source of carriers in the channel. A paper by Ibbetson, et al.,[1] explored this question theoretically and experimentally.

Introduction

Power MOSFETs are widely used with an inductive load for S/W power supplies, DC-DC converters, and so on. But due to high frequency operation, the surge voltage applied to the MOSFETs at turn-off depends on the inductance and parasitic inductance in the circuit. For some operation modes, the pulse width for the turn-on or off will be very short, and the device fails due to the short surge period.

Abstract

The measured I-V curve from a ten period Si/SiGe MQW pin LED fabricated using a UHVCVD system is compared with ATLAS simulation results. A sizable silicon emission peak is observed at high current injection mode at room temperature. This phenomena can be explained as follows: because of the hetero-junction between the top silicon buffer layer and MQW, when bias increases there is a potential barrier formed due to band bending. Thus there will be a large accumulation of holes in the buffer layer. The recombination rate in this layer increases which results in increased silicon light intensity.

For various technological reasons, LEDs and as well as photo-voltaic devices frequently use PEDOT:PSS on top of ITO contacts as a hole injecting or hole collecting layer, respectively. However, due to the presence of this layer, a direct parasitic current path opens up between the ITO contacts of neighboring pixels.