In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to implement the high-level description of the chip which is typically written in RTL. A synthesis tool such as Design Compiler or RTL Compiler is used to generate a gate-level netlist built out of the standard logic cells from a cell library. Communication on and off of the chip, requires unique input/output cells or I/Os that can drive off-chip wiring and withstand electrostatic discharges in the range of thousands of volts. The other main category is digital memories typically SRAMS that can take up a significant amount of area on the die for a chip. These 3 categories of digital design IP are called Foundation IP.
작성자: Ingrid Schwarz
저자는 아직 경력을 작성하지 않았습니다.
하지만, Ingrid Schwarz 씨는 무려 1784 항목에 기여한 것을 자랑스럽게 생각합니다.
엔트리 Ingrid Schwarz
2019년 8월 1일
In the world of SoC development, an IP management system is software for the licensing, distribution and compliance administration of design IP for both vendors and consumers of IP.
In May 2019 Silvaco was awarded a patent for System and Method for IP fingerprinting and IP DNA analysis. This patent reflects the unique technology inside the Xena® IP Management System from Silvaco.
2019년 7월 23일
In the following video, Dr. Firas Mohamed, VP & GM, Machine Learning & Flow Optimization Division and GM, Silvaco France talks with Graham Bell about Machine Learning technologies deployed in Silvaco EDA tools at the SEMICON West 2019, July 9 – 11 at Moscone Center in San Francisco. A transcript of the video is also below.
2019년 7월 17일
일시: 2019년 7월 12일 | 2:00am-2:30am (한국 시각)
실바코의 SIPware의 관련 표준 및 오토모티브 컨트롤러 IP의 기능에 대한 검토를 통해 자동차의 개별 부문과 동향에 대한 논의를 제시합니다.
I interviewed Silvaco partner Stephen Fairbanks, CTO of Certus Semiconductor from the show floor at DAC 2019, in Las Vegas, about I/O Design and Characterization. He talks about using the Viola characterization tool from Silvaco for a complex part while under time pressure to produce an accurate model. A full ranscript of the conversation is below.
New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.
2019년 6월 26일 | 2:00am-2:30am (한국 시각)
Verilog-A으로 SPICE 컴팩트 모델을 구현하기 위한 전문적인 가이드를 소개합니다.