In a previous article [1], the efficient use of the SmartSpice .MODIF statement for cell characterization was discussed. This article will focus on using advanced features of the SmartSpice scripting language to solve this problem in a more flexible manner.
Thin film transistors (TFTs) have an important application in the manufacture of active matrix LCD displays. As this technology has become more mature, a number of different models of both amorphous silicon (a-Si) and polysilicon TFTs have been proposed. Recently two new models developed by the Rensselaer Polytechnic Institute (RPI) have been implemented in the SmartSpice circuit simulator. These models are also now available in the TFT module of UTMOST III and this article will discuss the different model characteristics, and their use in both SmartSpice and UTMOST III.
The SmartSpice Interface to Cadence integrates the Analog Artist and Composer elements of the Cadence Design Framework II (DFII) with SmartSpice. This integration is accomplished, in versions 4.4.0 and later of DFII, through the Cadence Spice Socket (cdsSpice) and the OASIS interface in the Analog Artist and Composer components of DFII. Versions of DFII prior to 4.4.0 are also supported by SmartSpice, but these solutions rely on the older HSPICE Socket, and necessarily offer substantially less functionality than is provided by the current interface.
Ring oscillator circuits are a valuable test structure for determining the feasibility and success of an integrated circuit process fabrication sequence. One of the most useful results obtainable from a ring oscillator test structure is the delay time per gate.
The Berkeley BSIM3SOI model, released in December 1997, is now available within SmartSpice as the MOSFET level=25 model. This model incorporates three separate implementations: the original Berkeley model implementation is invoked with the selector Berk=2; the Silvaco implementation is invoked with Berk=-2.
The paper describes a generalization of the scanline approach [1] to reconstruction of the shape of planar object represented by a discrete point set with a given distance threshold d. This problem arises in applications of VLSI layout image processing, e.g., during automated reticle inspection.
This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension of capabilities of flat DRC systems. This technique makes it possible to report hierarchical errors in ordinary flat DRC systems.
One of the most challenging and time consuming tasks
in VLSI design automation is Layout Versus Schematic
(LVS). The problem is to test the consistency between
the actual circuit, represented by the layout, and the
nominal circuit upon which the design was based.
Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?
Recent additions to the ATLAS device simulation framework have added the ability to simulate 3D electrothermal effects in Giga3D and mixed circuit simulation with 3D device simulation in MixedMode3D. The new modules add to the existing 3D device simulation within ATLAS as shown in Figure 1.