The NAND Flash memory cell has been refined to reduce the bit cost, but the limit of its miniaturization has been reached due to the high electric field problem and the difficulty of lithography. On that account, three-dimensional stack cell structures have been adopted to achieve mass storage devices [1-3]. It has already been reported that the fabrication of 256Gbit NAND Flash memory with 48 stacked layers started on August in 2015 [4, 5]. For the fabrication of the stack structures, it is necessary to realize etching of deep holes. For examples, if using 30nm design rules and one layer thickness is 40nm, its depth becomes 1.92um. If the holes diameter is 100 nm, its aspect ratio becomes 19.2. Then, in the next generation, the 512 Gbit flash memory cell will need the deep hole with the aspect ratio of 38.4 for 3.84um-depth. For investigating more suitable process conditions or optimum etched topography, accurate three-dimensional etching simulation is required, but it takes a very long time to simulate this deep hole etching accurately if using usual simulation methods like the Monte-Carlo method, because the aspect ratio of this deep hole is very large and therefore, the flux calculation effort of enhancing ions and neutral radical species is enourmous for a reactive enhanced ion etching (RIE) model.

A power IGBT (Insulated Gate Bipolar Transistor) is conventionally made up of a repetitive array of homogenous IGBT cells. Such a homogenous configuration renders a uniform current flow across the active surface area of the IGBT chip when the IGBT is turned on. Under a short-circuit condition, however, the IGBT being turned on is exposed to a very high collector-to-emitter voltage. In this condition, the IGBT conducts a very high collector current, leading to correspondingly high power dissipation in the form of heat flowing uniformly across the chip. If the heating of the chip exceeds a critical level during a short-circuit operation, the device may fail or even get destroyed by local overheating in conjunction with the establishment of current filaments in a localized area, or the hot spots, within the device.

As the design technology for power devices, such as MOSFET, GTO, and IGBT has matured, the importance of large domain 3D TCAD simulation has increased rapidly. Distributed computing is one of the attractive solutions for such simulations, because the system’s performance and capability is not limited by the number of CPUs or the total amount of memory on a specific computer. This advantage of distributed computing is expected to be increasingly advantageous, as the size and mesh point count for these devices becomes ever larger.