I run DRC, find one-two violations, correct them, then I re-run DRC to check whether my corrections worked. However re-running on the whole design is time-consuming. How can I run DRC over a piece of the layout, in the vicinity of the introduced changes?
Rectangular partitionings form a mathematical base for many modern approaches to automation of VLSI design [1-3]. In particular, popular methodologies of hierarchical placement (by cell grouping / merging) as well as procedures of global routing and layout compression deal with partitions that can be hierarchically subdivided into components of bounded complexity.
In this paper we introduce one of the latest and most advanced features of Silvaco’s Expert Layout processor for Windows NT DRC Guard. DRC Guard is fully functional real-time design rule checker that works in background mode and makes extensive use of multithreading/ multiprocessor capabilities of operating system.
When using the analytical implant tables in ATHENA the default model for the lateral implant range assumes a gaussian profile with a standard deviation equal to the vertical standard deviation (delta Rp) read from the table. This approximation is reasonable for amorphous implant substrates.
The shrinking critical dimensions of modern technology place a heavy requirement on optimizing the etching of narrow mask opening. In addition the aspect ratio of etches has been increased requiring deeper etches along with the small CDs. The simulation of these process requires more advanced techniques than the directional rate-based etching found in the current versions of Elite. A more complete treatment involving calculation of the plasma distribution is required.
The ATLAS device simulation framework has been to improve the analysis the large signal transient behavior. These features include a simple specification for single frequency sinusoidal waveforms and frequency domain representation of large signal data. Applications include all classes of RF devices in both silicon and III-V technologies.
CLEVER is designed to model interconnect parasitics by simulating the back end processing steps of custom cells in three dimensions. A 3D process simulator is used to realisticly reproduce the effects of photolithography, deposition and etching on the resulting structure topography
The traditional Noise models in SPICE used two parameters (AF and KF) to model the noise level and the frequency dependency of flicker noise in MOS devices. There are three different standard models and they can be activated using the noise level selector parameter NLEV in SPICE.
Following the log file conversion tool for TonyPlot introduced with UTMOST 12.3.14.R1, new file formats have been added to UTMOST III’s printing and plotting options to make manipulating UTMOST generated data even easier.
The latest Berkeley BSIM3v3.2 model of June 16 1998 has been integrated into SmartSpice 1.5.5. The Silvaco implementation of the Berkeley BSIM3v3.2 model can be invoked by specifying the model selector LEVEL=8 and the version selector VERSION=3.2 in the .MODEL definition. This version is now used as the default BSIM3v3 model. Older BSIM3v3 models can be invoked by specifying VERSION=3.0 or VERSION=3.1.