HIPEX-Net: New SILVACO Full-Chip LPE Tool vs. Maverick
Introduction
SILVACO is releasing its new layout parameter extractor: HIPEX-NET. The new tool will replace Silvaco’s Maverick, which is a part of Guardian LVS/ERC. While being fully compliant with Maverick, HIPEX-NET has many advantages over Maverick. The comparison chart in Table 1 shows the critical features, which make HIPEX-NET much more powerful for layout verification than Maverick.
| Feature | HIPEX-NET | Maverick |
| SPICE netlist extraction | Hierarchical and flat | Flat only |
| Parameter extraction of transistors (MOSFET, MESFET, JFET, BJT) and design diodes, resistors, and capacitors | Yes | Yes |
| Integration with SILVACO layout editor, Expert | Yes | Yes |
| Hierarchical extraction | Yes | No |
| Advanced processing of net names | Yes | No |
| Schematic backannotation | Yes | No |
| Compatibility with HIPEX parasitic tools | Yes | No |
Table 1. HIPEX-NET vs. Maverick: features comparison chart
HIPEX-NET is a full-chip hierarchical netlist extractor. It can handle very complex layout hierarchy, this is in stark contrast to Maverick , where Maverick must flatten the layout. As a result,HIPEX-NET works much faster and needs less memory to process big hierarchical layouts. Today HIPEX-NET successfully extracts 10 million transistor layouts on Win32 platform, which provides only 2GB of virtual memory. The 64-bit version available for SunOS can handle much larger layouts.
