AI-Powered Surrogates: From Process Geometry to I‑V Curves

Abstract

Modern semiconductor development requires rapid exploration of large design spaces while maintaining the predictive accuracy of physics-based simulation. In this webinar, we demonstrate how to create interactive surrogates using FTCO workflows combining multiphysics simulations, data analytics and machine learning. FTCO enables engineers to transform simulation data into compact surrogate models that can be evaluated in real time for design exploration, optimization, and what-if analysis.

The webinar begins with the preparation of Design of Experiments (DOE) projects and the extraction of geometric and electrical response data from multiphysics TCAD simulations. We then show how structural surrogates can be generated from process simulation results, enabling interactive visualization of geometry evolution as process parameters vary. Next, we demonstrate electrical surrogates, where complete I‑V curves and device metrics are modeled and reproduced in real time.

Attendees will learn how machine-learning-assisted model generation, SHAP-based feature selection, prediction profilers, desirability optimization, and shareable XML model cards can dramatically reduce turnaround time while preserving insights from detailed multiphysics simulations. The result is a practical workflow for accelerating process development, device optimization, and manufacturing-aware technology exploration.

What You Will Learn

• How to generate surrogates from multiphysics simulations
• How to build structural surrogates from process simulation data
• How to create electrical surrogates that reproduce complete I‑V behavior
• How to perform feature selection, surrogate model generation, and optimization
• How to deploy and share across teams and computing environments

Presenter

Dr. Christian Caillat
Senior Staff CAE, Silvaco

Dr. Christian Caillat is based in Boise, ID. Prior to joining Silvaco in June 2023, he was with Micron Technology for 13 years, where he contributed to various projects including emerging memory program collaboration with imec, 3D NAND Cell team lead, and advanced memory modeling. Dr. Caillat holds an engineering degree in Electronics and a PhD in Microelectronics from the National Polytechnical Institute of Grenoble (France).

WHO SHOULD ATTEND:

Process engineers, design engineers, application engineers, product engineers fab engineers, and engineering management.