Vertical LOCOS Power Devices in Victory Process:
From 3D Process and Electrical Optimisation to High Speed, Full Chip Process Emulation
Introduction
There is a constant demand to lower the on-state resistance of devices, improving their energy efficiency as well as increasing their current handling capabilities whilst maintaining the desired breakdown voltage. However, a trade-off relationship exists between the on-state resistance and breakdown voltage. This is referred to as the silicon limit [1]. Attempts have been made to break the silicon limit. One such method proposed by several authors is the Vertical LOCOS MOS (VLOCOS) [2,3].
Such structures are relatively easy to simulate in 2D. However, the layout designs are inherently 3D [4]. Therefore it is critical that accurate and robust 3D simulations are undertaken to understand and fully optimize the electrical characteristics.
In this Simulation Standard article, a rigorous investigation is made into the effect that various different 3D corner designs have on device breakdown performance. The simulations are executed using Victory Process (VP), Silvaco’s fully three dimensional process simulation tool with 3D physical oxidation.
