エントリー - Graham Bell

Victory TCAD Suite: How to use it for fast, efficient, and accurate simulation of power semiconductor devices

Silvaco TCAD has been used by Tier 1 power device manufactures and designers for decades. The introduction of Victory Process, Victory Mesh, and Victory Device significantly increases the functionality and flexibility of the tool set available to designers. In this article we look at how some of the features of this suite of tools improve the efficiency of the design flow.

TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate

The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna switches which are compatible with multimode GSM/EDGE, TD/WCDMA, and LTE systems exhibit higher integration levels and have become the fastest growing mobile phone submarket. CMOS-SOI processes, especially with thin silicon, have the potential to rival the FoM that was traditionally feasible only with GaAs technologies.

Weebit Nanoとシルバコ、ReRAMの採用を促進するシミュレーションの新機能を開発

2020年2月19日 – 全世界の半導体業界に向け次世代メモリ・テクノロジの開発を行うWeebit Nano Ltd (ASX: WBT) と、電子システム設計用ソフトウェア、IP、サービスの世界的リーディング・プロバイダであるSilvaco Inc. (以下シルバコ) は、本日、Weebitのシリコン酸化物 (SiOx) 抵抗変化型メモリ (ReRAM) デバイスについて電気的振る舞いのモデリングに成功したことを発表しました。

シルバコTCAD: 入門と基礎 – チュートリアル – パートIII

この3部構成のウェビナーでは、シルバコTCADのソフトウェア・スイートを紹介し、入門用トレーニングおよびチュートリアルを提供します。このシリーズにより、複雑なTCADに対して適切なスタート地点から取り組み、確信を持ってTCADシミュレーションを成功させる方法を短期間で習得することが可能です。

IBIS Models in SmartSpice

The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which is affiliated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power/ground bounce, transmission lines…) on printed circuit boards (PCBs).

New Features in SmartSpice 2.3.4.C

A powerful new feature “Stop-Continue” has been added to SmartSpice to allow the user to suspend a transient simulation and investigate the output before resuming the simulation run from the suspended state. This allows generated data checks during the simulation run and therefore ensuring relevant simulation data is generated. This feature allows a user to check intermediate simulation results and/or save (if necessary) on the fly.

Spectre® Replacement in the Cadence Flow

Silvaco has always supported the Solaris based Cadence design environment for seemless SmartSpice integration. To accommodate new customer demands to support the new Linux environment, Silvaco has developed a SmartSpice interface for it. This new interface software allows users to replace Spectre with SmartSpice as the analog simulation engine without disrupting the design flow.