Silvaco TCAD has been used by Tier 1 power device manufactures and designers for decades. The introduction of Victory Process, Victory Mesh, and Victory Device significantly increases the functionality and flexibility of the tool set available to designers. In this article we look at how some of the features of this suite of tools improve the efficiency of the design flow.
The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna switches which are compatible with multimode GSM/EDGE, TD/WCDMA, and LTE systems exhibit higher integration levels and have become the fastest growing mobile phone submarket. CMOS-SOI processes, especially with thin silicon, have the potential to rival the FoM that was traditionally feasible only with GaAs technologies.
It is crucial for any kind of calculations that units are consistent between equations and modeling modules. Often different units are used in various experimental and theoretical fields. Therefore, we have introduced standardized unit conversions, making it possible to specify any desired units when changing parameters within the MATERIAL statement.
Victory Mesh initially supported loading and remeshing of the saved status from Victory Process. Victory Mesh 1.5.0 onwards is now able to load and remesh individual structure files (.str files), including associated scalar fields. These include the result of a device simulation from software such as Victory Device and Atlas.
2020年2月19日 – 全世界の半導体業界に向け次世代メモリ・テクノロジの開発を行うWeebit Nano Ltd (ASX: WBT) と、電子システム設計用ソフトウェア、IP、サービスの世界的リーディング・プロバイダであるSilvaco Inc. (以下シルバコ) は、本日、Weebitのシリコン酸化物 (SiOx) 抵抗変化型メモリ (ReRAM) デバイスについて電気的振る舞いのモデリングに成功したことを発表しました。
Feb. 5, 2020
On the 4 th and 5th of February 2020, in Montpellier (France), at the premises of LIRMM, CNRS the Kick-off meeting of NeurONN took place. All the Partners of the NeurONN Consortium met and set the ground for the activities along the three-year duration of the EU Project
この3部構成のウェビナーでは、シルバコTCADのソフトウェア・スイートを紹介し、入門用トレーニングおよびチュートリアルを提供します。このシリーズにより、複雑なTCADに対して適切なスタート地点から取り組み、確信を持ってTCADシミュレーションを成功させる方法を短期間で習得することが可能です。
The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which is affiliated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power/ground bounce, transmission lines…) on printed circuit boards (PCBs).
A powerful new feature “Stop-Continue” has been added to SmartSpice to allow the user to suspend a transient simulation and investigate the output before resuming the simulation run from the suspended state. This allows generated data checks during the simulation run and therefore ensuring relevant simulation data is generated. This feature allows a user to check intermediate simulation results and/or save (if necessary) on the fly.
Silvaco has always supported the Solaris based Cadence design environment for seemless SmartSpice integration. To accommodate new customer demands to support the new Linux environment, Silvaco has developed a SmartSpice interface for it. This new interface software allows users to replace Spectre with SmartSpice as the analog simulation engine without disrupting the design flow.