Effect of Fin Thickness on Subthreshold Characteristics of 10 nm FinFETs Using 3D TCAD

This work was submitted to Silvaco Inc. by Rochester Institute of Technology, Department of Electrical & Microelectronic Engineering.
Silvaco would like to thank the authors Abhijeet Walke and Santosh K. Kurinec

Introduction

The planar bulk Si metal-oxide semiconductor field-effect transistor (MOSFET) has reached its scaling limit due to various short channel effects (SCE). With 20 nm advanced planar technology, the source and drain encroached into channel resulting in off state leakage current. Tri gate FinFET devices have already replaced conventional planar MOSFETs for 14nm and beyond due to their superior control over the channel resulting in lower values of subthreshold swing (SS) and reduced drain induced barrier lowering (DIBL). Nevertheless, gate induced drain leakage is found to be the limiting factor in achieving ultralow (<100pA/um) values of IOFF. In this work, we have studied the effect of fin thickness on subthreshold characteristics of bulk nFinFET using three dimensional simulation.