Maverick– Hierarchcal Full-Chip Extractor Recent Significant Advances
Introduction
Maverick is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing CELEBRITY framework which includes state-of-the-art software for VLSI layout editing, hierarchical design rule checking and layout versus schematic comparison. The latest release of Maverick is equipped with many new interface features, including the ability to search for a net by name, and new engine upgrades, such as extraction of parameters of active devices. A new numerical procedure has been developed for resistance extraction of complex geometrical shapes.
Parameter Extraction
An important feature of any netlist extractor is the ability to accurately report geometrical active device parameters to the netlist.
For MOS technology, Maverick provides channel length (L), channel width (W), drain diffusion area (AD), source diffusion area (AS), perimeter of the drain junction including the channel edge (PD), perimeter of the source junction including the channel edge (PS).
For diodes, extraction is performed for the area of the diode (AREA) and perimeter of junction (PJ).
For capacitors, Maverick reports the capacitance combining inputs from the technology file with extracted geometries. To obtain the capacitance the technology file must include two technology constants: area capacitance (AreaAttr in aF/?m2) and perimeter capacitance per unit length (PerimAttr in aF/?m). These are supplied together with both layer names for the capacitor. A typical technology file input might be:
Capacitance
{
Layer1 = “Pin1”
Layer2 = “Pin2”
AreaAttr = 60
PerimAttr = 90
}
