Hints, Tips and Solutions – November 2006

Q. Is it possible to calculate the resistance components of a MOSFET (i.e. channel resistance, epi resistance, substrate resistance etc.) as a function of gate bias?

A. The resistance components of a MOSFET, Trench UMOS or LDMOS device can in general be obtained from the quasi-Fermi level potential and the terminal current.

To illustrate the resistance calculation, the standard example “mosfetex01.in” was used. A structure file is saved at a drain voltage of 0.1V and a gate voltage of 3V. In TonyPlot, plot the Net Doping contour as well as the Electrodes. Using the Cutline tool, do a horizontal cut across the device along the channel from the source to the drain.

Then using the “Function” options create a function that is defined by the electron QFL divided by the drain bias at the operating point. The drain bias is a constant that can be taken from either the run-time output or a plot of the log file. Plotting this function will give the cumulative resistance along the channel from the source to the drain.

You may also want to determine the channel resistance as a function of gate bias. To do this you can use the EXTRACT and PROBE statements as follows:

First, use the EXTRACT statement to obtain the locations of the junction edges. The following lines show how to obtain the locations of the junction edges 0.01 microns below the oxide interface.