Agenda subject to change.
Dr. Babak Taheri
Chief Executive Officer and Director, Silvaco
Babak A. Taheri, Ph.D. has served as Chief Executive Officer and a board member of Silvaco since August 2019, with a brief pause between September and November 2021. Prior to becoming CEO, he served as Chief Technology Officer and Executive Vice President of Products from October 2018 to August 2019.
Before joining Silvaco, Dr. Taheri was the CEO and President of Integrated Biosensing Technologies (IBT), an advisory and consulting firm, from May 2015 to October 2018. Dr. Taheri serves on the board of directors of Sunright Limited (Singapore: SGX), a provider of advanced semiconductor test and burn-in services. He has also served on advisory boards, including MEMS World Summit, Novasentis, AGCM, ALEA Labs, Silverlake Sumeru, Lion Point Capital, and was a member of the governing council of ESDA Alliance (2019-2021). He currently chairs the advisory board for the Electrical Engineering Department at the University of California, Davis.
Dr. Taheri has held leadership roles at several companies, including VP & GM at Freescale Semiconductor (now NXP), where he received the “Diamond Chip Award” (2013, 2014) and was named MEMS & Sensors Executive of the Year (2014). He has also served as VP/GM at Cypress Semiconductors, earning “The Perfect Project Award” in 2003, and was instrumental in acquiring Ramtron for the business he was managing. His experience includes roles at Invensense (now TDK), SRI International, and Apple.
Dr. Taheri holds a B.S. in Engineering from San Francisco State University, an M.S. in Electrical Engineering from San Jose State University, and a Ph.D. in Biomedical Engineering (with concentrations in Electrical Engineering and Neuroscience) from the University of California, Davis. In 2015, he received the Distinguished Engineering Alumni Medal (DEAM) from UC Davis. His most recent book, “Artificial Sensors Shape the Six Pillars of Our Lives,” was published in 2021.
Wally Rhines
President and CEO of Cornami and Silvaco Board Member
Walden C. Rhines, Ph.D., has served as a member of our board of directors and as a member of our audit committee since September 2022. Since March 2020, Dr. Rhines has served as President and Chief Executive Officer of Cornami, Inc., a fabless semiconductor company. Since 2015, Dr. Rhines has also served as a member of the board of directors and as chair of the compensation committee of Qorvo, Inc. (Nasdaq: QRVO), a semiconductor company, since January 2015 and its chairman since November 2023. He served as a member of the board of directors of PTK Acquisition Corp. (NYSE: PTK), a special purpose acquisition company from July 2020 until September 2021 and served on its audit, nominating and compensation committees. From October 1993 to March 2017, Dr. Rhines served as President and Chief Executive Officer of Mentor Graphics Corporation, an EDA company, and chairman of its board of directors from 2000 until its acquisition by Siemens in March 2017, pursuant to which the company was renamed Mentor Graphics, a Siemens Business. Following the acquisition, Dr. Rhines served as President and Chief Executive Officer of Siemens EDA (formerly Mentor Graphics, a Siemens Business), from March 2017 to October 2018, after which he served as its Chief Executive Officer Emeritus until September 2020. Dr. Rhines received a B.S.E. in metallurgical engineering from the University of Michigan, an M.S. and Ph.D. in materials science and engineering from Stanford University, and a M.B.A. from the Southern Methodist University, Cox School of Business.
Dr. Peter Griffin
Dr. Peter Griffin is an expert in microfabrication, having co-authored one of the most widely used textbooks in the area with Prof. Jim Plummer titled “Integrated Circuit Fabrication – Science and Technology” published by Cambridge University Press in 2024. He has significant hands-on experience in simulating and building semiconductor structures and teaching semiconductor technology courses at Stanford.
For the past two decades, he has performed interdisciplinary work at the Stanford Genome Technology Center (SGTC) with a particular emphasis on digital microfluidics. He is particularly interested in how semiconductor technology can contribute to bioengineering and was the lead author on major DARPA, NIH and SRC grants in various application areas. Griffin has enjoyed long term collaborations with leading researchers on those interdisciplinary grants which has made his time at Stanford very productive. Griffin’s current interest is on impedance measurements for diagnostics in the laboratory of Prof. Lars Steinmetz at SGTC.
Dr. Guichard will provide an update on Silvaco TCAD Victory simulation products, the importance of TCAD in the development of next-generation devices, and the future of TCAD development.
Dr. Eric Guichard
SVP and GM of TCAD Business Unit – Silvaco
Eric Guichard, Ph.D., has served as our Senior Vice President and General Manager of our TCAD division since November 2012, and served as our Vice President of Applications from July 2008 to November 2012. From September 1995 to July 2008, Dr. Guichard served in various roles with Silvaco SA, formerly known as Silvaco Data Systems, one of our wholly-owned subsidiaries, including as an applications engineer. Dr. Guichard received a M.S. in material science and a Ph.D. in semiconductor physics from Instituto Politécnico Nacional de Grenoble, France.
Quantum effects dominate at the nanoscale, where classical simulation tools lack the capability to accurately capture or observe these phenomena. Ciena’s analog design process relies significantly on provided models; however, as we scale, these models become increasingly less accurate. Consequently, we have initiated analysis and verification efforts to develop our own models to account for quantum effects. Additionally, we are required to analyze device behavior at cryogenic temperatures used in qubit technology.
Quantum device modeling requires specialized tools that can solve the Poisson-Schrödinger equations self-consistently. Silvaco’s Victory Atomistic tool easily met our initial requirements, but we quickly identified additional complexities, which prompted a close collaboration between Silvaco and Ciena teams to refine and enhance the tool.
Through this collaboration, we have developed an engine that closely simulates our in-house devices. Despite limited information about the fabrication process, we worked diligently to design a device model that approximates Ciena’s actual devices. While the model does not replicate measurements exactly, the trend of Victory Atomistic’s simulation graphs aligns well with the lab data for our 5nm devices at room temperature.
In advancing our qubit technology research, we successfully measured and observed device behavior at extremely low temperatures; however, the process was both costly and complex. To streamline our approach, we are working to replace physical measurements with device simulations, and Silvaco’s ViA shows promising potential in this area. At these extreme low temperatures, the tool initially faced numerical convergence issues, but with iterative improvements, these challenges are gradually being resolved. Future work will focus on further enhancing ViA, particularly to achieve stable convergence at lower cryogenic temperatures and lower bias conditions.
Sanam Moslemi-Tabrizi
Analog Engineer, Ciena
Bio Sanam Moslemi-Tabrizi received her B.Eng. in Electrical Engineering from Tabriz University in 1996, specializing in Analog Circuits. She completed her M.Sc. in Electrical Engineering at Concordia University in 2007, focusing on Solid State Devices. Her master’s thesis in Computational Quantum Mechanics involved computing eigenstates for multidimensional nanostructures.
As a Research Associate in the Department of Electronics at Carleton University, Sanam conducted significant research in electromagnetics, where she developed a Full Vectorial Mode Solver and Waveguide Simulator based on Yee cell Finite-Difference Frequency-Domain (FDFD) methods. This tool supported her work in designing a 2D beam-scanning system based on Optical Phased Array (OPA) technology for LiDAR applications.
Currently, Sanam is an Analog Engineer at Ciena, responsible for the verification of analog circuits and for development of advanced quantum device models for Ciena’s next-generation products.
This talk will explore advancements in plasma etching process optimization for process technology computer-aided design (TCAD), focusing on the integration of multi-scale modeling with AI-driven techniques. Key topics will include the development of equipment-informed feature-scale models, utilizing machine learning (ML) to bridge the gap between reactor and feature scales in plasma chambers. This approach supports predictive modeling for high-aspect-ratio (HAR) structures, critical for complementary metal-oxide-semiconductor (CMOS) applications and emerging device architectures.
A primary challenge in optimizing plasma etching processes is synchronizing the complex plasma chamber conditions across scales. We will discuss recent progress in creating surrogate models using equipment simulations such as the Hybrid Plasma Equipment Model (HPEM). Machine learning-based surrogate models, combined with available experimental data, can assist in an efficient generation of flux predictions. These models facilitate rapid feature-scale adjustments, fostering a digital twin environment with the potential for real-time optimization.
Ultimately, the proposed workflows have the potential to merge complex plasma chamber environments to TCAD, significantly reducing reliance on trial-and-error experimentation. This could lead to a more streamlined, efficient, and greener semiconductor manufacturing process.
Dr. Lado Filipovic
Associate Professor and the Director of the Silvaco-supported Christian Doppler Laboratory for Multi-Scale Process Modeling of Semiconductor Devices and Sensors at the Institute for Microelectronics, TU Wien
Lado Filipovic is an Associate Professor and the Director of the Silvaco-supported Christian Doppler Laboratory for Multi-Scale Process Modeling of Semiconductor Devices and Sensors at the Institute for Microelectronics, TU Wien. His research focuses on advanced process modeling, technology computer-aided design (TCAD), and integrated semiconductor sensors. Dr. Filipovic obtained his habilitation in Semiconductor Based Integrated Sensors and his doctoral degree in Microelectronics from TU Wien in 2020 and 2012, respectively.
Dr. Filipovic leads a diverse portfolio of research projects covering the full spectrum of technology readiness levels (TRLs), supported by the Austrian Science Fund (FWF), the Christian Doppler Research Association (CDG), the Austrian Research Promotion Agency (FFG), and the European Union, as well as through direct industry collaborations. A Senior Member of IEEE, Dr. Filipovic actively serves on Technical Program Committees for prominent IEEE conferences such as IEDM and SISPAD. His group has also released several open-source tools, including the process simulator ViennaPS, utilized by academia and industry for nanoelectronic device studies.
Currently collaborating with industry partners like Silvaco, Fuji Electric, Infineon, as well as academic institutions worldwide (e.g., MIT, University of Glasgow, Arizona State University, Chinese Academy of Sciences), Dr. Filipovic’s research delves into enabling multi-scale modeling of semiconductor device fabrication and operation. His group is also investigating the integration of van der Waals layered materials (2D materials), including graphene and MoS2, for advanced sensing applications.
The common approach to optimize a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach.
This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically, it can take weeks to months of experimentation, depending on what process parameters are not meeting their targets.
A new approach already in production use today leverages artificial intelligence (AI) and machine learning (ML) to generate an accurate simplified model of a fabrication step.
Silvaco’s FTCO Platform incorporates Machine Learning to accelerate semiconductor Digital Twin development. With Silvaco’s platform you can input your fabrication data and TCAD data to start building out an ML model.
This presentation will showcase this FTCO flow with examples to give you more insight into this flow and how you can apply it for you and your team’s needs.
Dr. Christian Caillat
Senior Staff CAE, Silvaco
Bio Dr. Christian Caillat is a Senior Staff CAE at Silvaco, based in Boise, ID. Prior to joining Silvaco in June 2023, he was with Micron Technology for 13 years, where he contributed to various projects over the years, including emerging memory program collaboration with imec, 3DNAND Cell team lead, advanced memory modeling.
Dr Caillat holds an engineering degree in Electronics and a PhD in Microelectronics from the National Polytechnical Institute of Grenoble (France).
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Dr. David Green
Senior Field Applications Engineering, Silvaco
Dr. David Green is a Senior Field Applications Engineering for Silvaco, based in Cambridge, UK. He has been with Silvaco for 18 years, with responsibilities including pre/post sales support of TCAD customers in EMEA and development, as well as management of R & D TCAD projects. He provides support on a wide variety of applications including power, display, reliability, and optical.
His PhD and subsequent post-doctoral work involved the design, simulation, development, and testing of vertical and lateral power devices for integrated circuits.
In this presentation, we start by introducing the SPICE modeling of power devices for different technologies including Si, GaN, and SiC, by using various methodologies such as compact models, Verilog-A and macromodels.
Then, a significant portion of our presentation will be dedicated to illustrating the Spice modeling of a SiC DMOS in detail. The modeling flow will cover how to use the device I-V and C-V data, by also properly addressing its specific bias-dependent capacitances. Furthermore, we will exemplify how to deal with model tuning based on dynamic characteristics. Finally, we will also demonstrate how to also consider the dynamic temperature effects.
Dr. Bogdan Tudor
Head of Silvaco’s Device Characterization Group
Dr. Bogdan Tudor is Head of Silvaco’s Device Characterization Group. He is responsible for all aspects of the Device Characterization Group’s activities, including R&D, field operations and modeling services. He joined Silvaco in 2017. Prior to joining Silvaco, Dr. Tudor was a Principal Software Architect at ProPlus Design Solutions for 4 years and before that he was a Senior R&D Engineer with Synopsys for 12 years. Dr. Tudor has an extensive expertise in Device characterization, Compact Model development, MOSFET Aging Reliability Analysis and Software development. Dr. Tudor holds a MS in Electrical Engineering and a Ph.D. in Microelectronics from the Polytechnic University in Bucharest, Romania.
Dan FitzPatrick and Ben Louie will provide an update on Silvaco’s Analog Custom Design product portfolio, new features and functionality, and the future of Silvaco’s EDA solutions.
Dan FitzPatrick
VP and GM of EDA Business Unit – Silvaco
Dan FitzPatrick is Vice President and General Manager of the EDA Business Unit. He is responsible for managing the development of all EDA tools including analog custom design and verification, circuit simulation and SPICE modeling, standard cell layout generation and characterization and SIP management tools. Dan joined Silvaco in 2021, leading SIP management, standard cell layout generation and characterization product lines. Dan has an extensive EDA background and many years of experience in software development and product management from startups to fortune 500 companies. Dan holds a MSEE from the University of Florida and an MBA from the University of Central Florida.
Ben Louie
VP and GM of IP Business Unit – Silvaco
Ben Louie is Vice President and General Manager of the IP Business Unit responsible for managing all semiconductor design IP. He has over 22 years of experience in Memory design encompassing NOR Flash, NAND Flash, and MRAM. Before joining Silvaco, Ben made significant contributions to semiconductor startups such as Spin Memory, Zeno Semiconductor, and MagSil. His expertise also extends to established industry players, having worked at Micron Technology and Xilinx. At Micron Technology, Ben led the Design team in the transition from NOR flash to NAND flash and was the design lead/manager for their first NAND products. Ben holds a Bachelor of Science Degree in Electrical Engineering and a Master of Science Degree in Electrical Engineering from Santa Clara University. He has been issued 123 US Patents.
In discrete power device development, physical design and verification are essential for ensuring performance, reliability, and manufacturability. This presentation explores how Silvaco’s Expert Layout Editor and SmartDRC streamline the physical design process, particularly for complex power device geometries, which often involve also numerous curved shapes. The session will highlight Expert’s capabilities for efficient layout creation, as well as SmartDRC’s high performance in verifying layouts with many curved geometries, commonly a challenging aspect for DRC (Design Rule Checking) engines, while ensuring both accuracy and speed. The integration of Silvaco’s broader flow, combining TCAD and EDA, will also be briefly introduced, a unique offering in the market for power devices, allowing customers to rely on a single vendor for both aspects.
Stefano Pettazzi
Staff Applications Engineer, Silvaco, Inc.
Stefano Pettazzi holds an M.S. degree in Electrical and Electronics Engineering from the University of Pavia, Italy. With nearly 25 years of experience in EDA and microelectronics companies, he has been with Silvaco since 2012, serving as a Staff Applications Engineer, supporting EDA software for both front-end and back-end design flows.
Chung-Chun Chen, Director of Analog Design
Silicon Creations
Chung-Chun (CC) Chen has been with Silicon Creations since 2011 and is a principal circuit architect for SerDes IO interface. Currently, CC leads SerDes team as a Director of Analog/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia since being back in 2019. During 2018 – 2019, CC joined Ubilinx Technology (Realtek Semiconductor Group) in San Jose, CA, and he was the driver/architect of Realtek’s high-speed Serdes technologies. During 2011 – 2018, CC was a senior analog designer/manager at Silicon Creations in Atlanta, Georgia while he designed analog IP products including Ring-based & LC tank PLLs, Serializer, De-serializer with all clocking building blocks (PLL/CDR, phase interpolator) and equalization (FFE, CTLE, DFE) circuitry. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia. Prior to this, he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.
Chung-Chun (CC) Chen (S’02–M’09–SM’17) was born in Taipei, Taiwan, in 1979. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2004 and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.
In advanced technology nodes the impacts of parasitics in a design can be severe. Using simulations to identify and investigate such impact can be long and laborious. Viso is capable of tackling these issues and speed-up parasitics analysis. Viso is an advanced parasitics analysis solution to quickly analyze RC parasitic networks. Viso handles advanced nodes effortlessly, and its intuitive user interface allows to easily highlight and identify parasitics issues in the design. Viso features multiple analysis to obtain accurate information of the parasitics network, like timing estimations, crosstalk effects and matching between different nets. Such results can then be used to pinpoint troublesome areas in the design.
Here we will demonstrate how Viso can be used to investigate RC parasitic issues in high-speed circuits without the need of multiple iterations of long simulations.
Carlos Augusto Berlitz, PhD
Corporate Application Engineer (CAE), Silvaco Inc.
Carlos Augusto Berlitz, PhD, is a Corporate Application Engineer for RC parasitics analysis and reduction EDA solutions at Silvaco. He is responsible for providing support, test and contribute to the roadmap of the EDA tools for RC parasitics analysis and reduction. He worked in circuit design and support in different companies. Dr. Berlitz joined Silvaco’s EDA team in 2023.
He holds a PhD in Electronics, Electrotechnics, Automation and Signal Processing from INSA Lyon, France, an MS in Electrical Engineering from Grenoble Alpes University (UGA), France, and a BS in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Brazil.
As an active semiconductor foundry, process or technology development and enhancement is frequent. To meet and verify the enhancement on library, library optimization and validation is needed. In this presentation, we share specific contributions of Silvaco tools in overcoming the current challenges during SilTerra’s IP library development process in a unique, dynamic way to realize the optimization and validation, which ultimately results in reducing characterization timing.
Siti Mariyam
IP Senior Engineer, SilTerra Malaysia Sdn. Bhd
Education : Bachelor of Electronics System Engineering University of Technology Malaysia (UTM) , Malaysia
Skill Set and Expertise : Standard Cells & IO Library Development and Silicon Validation
The transition to advanced FinFET technology nodes brings a new set of challenges and opportunities to digital circuit design, particularly for low-voltage applications. This presentation examines the unique characteristics and complexities of FinFETs at these nodes, with a focus on standard cell design and operation in low-voltage environments. We will explore the impact of these challenges on key metrics like area, timing, power, variability, and how they influence the design of standard cells optimized for ultra-low voltage functionality.
Silvaco’s portfolio of low-voltage standard cell libraries for advanced FinFET nodes is introduced as a comprehensive solution to meet rigorous power and performance demands. This portfolio includes specialized offerings such as multi-bit flip-flops, retention flip-flops, high fan-in cells with reduced transistor stacks, and an extensive Power Management Kit (PMK). Designed for efficiency and reliability under reduced supply voltages, these libraries leverage multi-threshold options to enable a tailored balance between performance and power consumption. This presentation provides a technical foundation for design engineers tackling the stringent requirements of advanced FinFET nodes in low-voltage applications.
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Fernando Carrion
Design Engineer, Silvaco
Fernando Carrion is an electrical engineer graduated from The Federal University of Rio Grande do Sul (UFRGS) and an Analog Circuit Designer certified by the IC Brazil program. He is currently a Design Engineer at Silvaco, with over 4 years of experience in standard cell design and characterization.
Felipe will demonstrate how Cello FinFET streamlines library development for advanced nodes. We’ll explore how to leverage existing libraries for new nodes and use automation to efficiently generate GDSII from CDL files. Attendees will gain practical insights into using Cello FinFET to accelerate library development and enhance productivity in advanced node design.
Felipe Bortolon
Standard Cell Library IP, Silvaco
Felipe Bortolon is the Engineering Manager for the standard cell layout automation framework – Cello. He holds a Computer Engineering degree from PUCRS and a MSc in Microelectronics from UFRGS, Brazil.
A capless LDO providing up to 30 mA load current has been designed in TSMC N3P 3nm FinFET process. The output voltage of the LDO is programmable from 0.45 V to 0.9 V with 50mV increments and an input voltage is 1.2V +/- 10 %. Very good PSRR (> 40 dB @ 1KHz and > 29 dB @ 10 MHz) and load regulation (< 18 mV undershoot/overshoot for 1A/ns load transient) across all PVT corners (temperatures ranging from -40°C to 125°C) were achieved with compact area (< 3400 sq um).A Bandgap Voltage Reference is a voltage reference circuit widely used in integrated circuits producing an almost constant voltage, with very little fluctuations from variations of power supply, load, time, temperature and process. Silvaco developed low and higher voltage Bandgap voltage references delivering 0.45 V and 0.92 V respectively with only 1% variation across -45°C to 150°C. The circuits have been designed in the TSMC N3P 3nm FinFET technology.
Speaker Name Ahmad S. Mazumder
Director of Engineering, Silvaco
Ahmad S Mazumder is a Director of Engineering in the IP Division of Silvaco. He is responsible for Development & Customer support in all Analog and Interface IPs. He is an Industry veteran on the development of High-Speed Memory & Interface IPs and all sorts of analog IPs. He worked on cutting edge DDR, extreme High-speed SerDes, Interfaces, ESD, Quality & Reliability for 28 years at various SOC companies – Intel, Broadcom, C-Cube Microsystems etc. He joined Silvaco’s IP Engineering Division in 2019 and is Instrumental in growing Analog/IP business at an accelerated rate.
Ahmad S Mazumder holds an MS in VLSI Semiconductor Design from the City University of New York and BS in Electrical & Electronics Engineering from Bangladesh University of Engineering and Technology.
Shaikh A Shams
Staff Engineer, Silvaco
Shaikh A Shams is a Staff Engineer in the Analog/Interface IP Division of Silvaco. He is responsible for developing Analog and Interface IPs at Silvaco. He worked on High-speed SerDes, Interfaces, Voltage Regulators, AMS Design and Verification for 22 years at different companies – Intel Corporation, Global Foundries and Dialog Semiconductor. He joined Silvaco’s IP Engineering Division in 2020. Shaikh A Shams holds an MS in Electrical and Computer Engineering from the University of Arizona.
This presentation provides an overview of the Controller Area Network (CAN) protocol and its evolution, culminating in CAN XL, which enhances efficiency and connects to Ethernet standards like 10BASE-T1, addressing the needs of modern automotive communication, including Software-Defined Vehicles. The evolution began in 1986 with the original CAN protocol, which featured non-destructive arbitration, allowing high-priority frames to access the bus while disconnecting faulty nodes to maintain communication integrity. Initially designed for automotive applications, CAN’s limitations in data throughput became clear with larger electronic control unit (ECU) data packages. In response, the CAN FD (Flexible Data-rate) protocol was introduced in 2011, supporting data rates up to 8 Mbps and a payload of 64 bytes. Finally, the third generation, CAN XL, enables a maximum payload of 2048 bytes at speeds up to 20 Mbps.
Antonio Mauricio Brochi
Director of Automotive IP, Silvaco
Bachelor’s degree in electronic engineering by the University of Campinas, Sao Paulo, Brazil. More than 30 years’ experience in SoC Systems and IP with focus on Automotive and Industrial applications. Worked for Motorola/NXP participating in the development of Microcontroller Cores, CAN Controllers, Automotive Timers, Cryptographic Accelerators and Low Power Controller, among others