• 技术刊物 Simulation Standard

Simulation Standard

Silvaco面向半导体工艺和器件仿真工程师推出的技术刊物

Expert Layout Editor – New Commands Focus On Easier Operation

Expert layout editor version 4.0.1R has several new commands and functions released together with the new Qt GUI interface. Most of them are developed in order to improve easier operation.

Every time I create a new project or library, an empty cell with the same name is created in my project

Q. Every time I create a new project or library, an empty cell with the same name is created in my project. What do I need to setup to avoid the creation of this empty cell?

STELLAR – Process Based Parasitics Capacitance Extraction on Large Custom Cells

SILVACO has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit and chip design.

LPE Optimization with Clever/Hipex/Exact Linkage Methodology

On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI design of rules measuring 0.13 um or lower. The quantitative consideration of coupling capacitance based on three-dimensional calculation is indispensable. Conventional advanced LSI design tools and methodology are limited in their ability to optimize the LPE library. As a result, the discussion of LPE tool accuracy and extracted parasitic results lack significant quantitative generality.

When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers

When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers, convergence can be a real problem. Previous methods suggested in the hints and tips archive of Silvaco’s simulation standard have made use of Silvaco’s Luminous module where a small amount of light intensity is incident on the device, the idea being to generate a small amount of carriers to aid convergence.

IBIS Models Now Supported in SmartSpice

Expert Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as enclosure wires, offset wires and sets of rectangles. Pwire objects enable extremely quick and efficient creation and editing of guard rings and shielded paths which are increasingly important due to higher integration density of IC designs.